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High aspect ratio contacts 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-029/40
출원번호 US-0569561 (2009-09-29)
등록번호 US-8093725 (2012-01-10)
발명자 / 주소
  • Wilson, Aaron R.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Brooks Cameron & Huebsch, PLLC
인용정보 피인용 횟수 : 15  인용 특허 : 15

초록

A contact formed in accordance with a process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an as

대표청구항

1. A contact formed in accordance with a process for etching an insulating layer comprising: first exposing the insulating layer to a second plasma of a second gaseous etchant comprising Ar, Xe, and combinations thereof to form an opening having an aspect ratio of less than 15:1; andsecond exposing

이 특허에 인용된 특허 (15)

  1. Donohoe, Kevin G.; Abatchev, Mirzafer; Veltrop, Robert, Aspect ratio controlled etch selectivity using time modulated DC bias voltage.
  2. Kwean, Sung-Un; Hwang, Jae-Seung, Etching gas composition for silicon oxide and method of etching silicon oxide using the same.
  3. Blalock, Guy T., High accuracy via formation for semiconductor devices.
  4. Hills Graham ; Nguyen Thomas D. ; Keil Douglas ; Khajehnouri Keyvan, Mechanism for bow reduction and critical dimension control in etching silicon dioxide using hydrogen-containing additive gases in fluorocarbon gas chemistry.
  5. McReynolds Darrell, Mechanism for etching a silicon layer in a plasma processing chamber to form deep openings.
  6. Ikegami Naokatsu,JPX, Method for forming contact hole by dry etching.
  7. Liu Guo-Lin,JPX ; Uchida Hidetsugu,JPX ; Aikawa Izumi,JPX ; Ikegami Naokatsu,JPX ; Hirashita Norio,JPX, Method for testing semiconductor device.
  8. Ikeda, Takenobu; Tadokoro, Masahiro; Izawa, Masaru; Yunogami, Takashi, Method of manufacturing a semiconductor integrated circuit device.
  9. Podlesnik, Dragan; Lill, Thorsten; Chinn, Jeff; Pan, Shaoher X.; Khan, Anisul; Li, Maocheng; Wang, Yiqiong, Method of micromachining a multi-part cavity.
  10. Coburn John W. ; Donohoe Kevin G., Plasma etching method using low ionization potential gas.
  11. John W. Coburn ; Kevin G. Donohoe, Plasma etching method using low ionization potential gas.
  12. Cohen,Barney M.; Ngan,Kenny King Tai; Li,Xiangbing, Plasma preclean with argon, helium, and hydrogen gases.
  13. Osborn William G. (Stamford CT), Re-insulation of conductor junctions of primary conductors.
  14. Kotecki David E. ; Nguyen Son V., Semiconductor device with high dielectric constant insulator material.
  15. Vaartstra Brian A., Supercritical compositions for removal of organic material and methods of using same.

이 특허를 인용한 특허 (15)

  1. Sel, Jongsun; Park, Chan; Suyama, Atsushi; Yu, Frank; Ogawa, Hiroyuki; Honma, Ryoichi; Yamaguchi, Kensuke; Iuchi, Hiroaki; Takeguchi, Naoki; Pham, Tuan; Sakakibara, Kiyohiko; Chen, Jiao, Blocking oxide in memory opening integration scheme for three-dimensional memory structure.
  2. Sharangpani, Rahul; Makala, Raghuveer S.; Koka, Sateesh; Matamis, George, Fluorine-free word lines for three-dimensional memory devices.
  3. Oginoe, Tomohiro; Honma, Ryoichi; Terahara, Masanori, Metallic etch stop layer in a three-dimensional memory structure.
  4. Ikawa, Yusuke; Sakakibara, Kiyohiko; Takii, Eisuke; Kajiwara, Kengo; Shimabukuro, Seiji; Matsudaira, Akira; Ogawa, Hiroyuki, Method of reducing control gate electrode curvature in three-dimensional memory devices.
  5. Yada, Shinsuke; Kamiya, Hiroyuki, Methods of fabricating memory device with spaced-apart semiconductor charge storage regions.
  6. Kanakamedala, Senaka Krishna; Zhang, Yanli; Makala, Raghuveer S.; Lee, Yao-Sheng; Alsmeier, Johann; Matamis, George, Methods of making three dimensional NAND devices.
  7. Makala, Raghuveer S.; Lee, Yao-Sheng; Kanakamedala, Senaka Krishna; Zhang, Yanli; Matamis, George; Alsmeier, Johann, Methods of making three dimensional NAND devices.
  8. Pachamuthu, Jayavel; Alsmeier, Johann; Matamis, George; Chien, Henry, Methods of selective removal of blocking dielectric in NAND memory strings.
  9. Kamiya, Hiroyuki; Yamaguchi, Kensuke, Selective floating gate semiconductor material deposition in a three-dimensional memory structure.
  10. Amano, Fumitaka; Ishikawa, Kensuke; Inoue, Shinya; Sano, Michiaki, Semiconductor device containing multilayer titanium nitride diffusion barrier and method of making thereof.
  11. Wada, Takayuki; Fujino, Shigehiro, Three dimensional NAND string with discrete charge trap segments.
  12. Hinoue, Tatsuya; Obu, Tomoyuki, Three-dimensional memory device containing fluorine-free tungsten—word lines and methods of manufacturing the same.
  13. Peri, Somesh; Koka, Sateesh; Makala, Raghuveer S.; Sharangpani, Rahul; Baenninger, Matthias; Pachamuthu, Jayavel; Alsmeier, Johann, Three-dimensional memory structure with multi-component contact via structure and method of making thereof.
  14. Ishigaki, Toru, Three-dimensional memory structures with low source line resistance.
  15. Tsutsumi, Masanori; Yada, Shinsuke, Uniform thickness blocking dielectric portions in a three-dimensional memory structure.
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