초록 ▼

A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparato

A time to digital converter (TDC) is able to be utilized for measuring a time interval between two signals with a very fine time resolution, which is defined as the difference in propagation delay per stage between two rings or chains of delay stages. The Vernier ring TDC, Vernier TDC with comparator matrix or Vernier ring TDCs with comparator matrix comprise two rings or chains of delay stages with slightly different propagation delays per stage and a plurality of comparators for comparing two signals propagation along two rings or chains and determining when the lag signal passes the lead signal. The lead and lag signal are initiated by two events and are each fed into a separate one the first stages of one of the specified rings or chains. The comparators are able to be organized in a comparator matrix in order to occupy less space and permit reuse. As a result, the input time interval (the time between the two initiating events) is able to be measured through the product of the time resolution and the number of stages through which the two signals propagated.

대표청구항 ▼

1. A ring time-to-digital converter comprising: a. a lead initiating stage for receiving a lead step signal and a lag initiating stage for receiving a lag step signal;b. a plurality of serially coupled lead delay stages for enabling propagation of the lead step signal, wherein a last lead delay stag

1. A ring time-to-digital converter comprising: a. a lead initiating stage for receiving a lead step signal and a lag initiating stage for receiving a lag step signal;b. a plurality of serially coupled lead delay stages for enabling propagation of the lead step signal, wherein a last lead delay stage is coupled to an input of the lead initiating stage and a first lead delay stage is coupled to an output of the lead initiating stage thereby forming a lead ring; andc. a plurality of serially coupled lag delay stages for enabling propagation of the lag step signal, wherein a last lag delay stage is coupled to an input of the lag initiating stage and a first lag delay stage is coupled to an output of the lag initiating stage thereby forming a lag ring; wherein each lead delay stage has a corresponding lag delay stage. 2. The converter of claim 1 wherein the lead step signal propagates from the lead initiating stage along the lead ring and the lag step signal propagates from the lag initiating stage along the lag ring. 3. The converter of claim 2 wherein each lead delay stage has an adjustable lead propagation delay interval that is greater than an adjustable lag propagation delay interval of each lag delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 4. The converter of claim 3 further comprising a plurality of comparator pairs, wherein each pair is coupled to a lead output of a lead delay stage and a lag output of the corresponding lag delay stage. 5. The converter of claim 4 wherein the plurality of comparator pairs each comprise an A-type comparator for detecting a lead or lag rising edge and a B-type comparator for detecting a lead or lag falling edge. 6. The converter of claim 5 wherein outputs of the A-type comparators toggle between a logical one and a logical zero when the lag rising edge arrives before the lead rising edge, and outputs of the B-type comparators toggle between a logical one and a logical zero when the lag falling edge arrives before the lead falling edge. 7. The converter of claim 6 wherein the comparators comprise any combination of singled-ended or differential arbiters, flip flops and latches. 8. The converter of claim 7 wherein the delay stages comprise any combination of inverters, buffers and any other type of logic gate. 9. The converter of claim 8 wherein the initiating stages comprise any combination of NAND gates, multiplexers, multi-switches or any other type of logic gate able to initiate the propagation of signals. 10. The converter of claim 3 further comprising a plurality of double-edge-triggered comparators, wherein each comparator is coupled to a lead output of a lead delay stage and a lag output of the corresponding lag delay stage. 11. The converter of claim 10 wherein outputs of the comparators toggle between a logical one and a logical zero when either the lag rising edge arrives before the lead rising edge or the lag falling edge arrives before the lead falling edge. 12. The converter of claim 1 wherein the lead initiating stage comprises one of the lead delay stages and the lag initiating stage comprises one of the lag delay stages such that the lead and lag initiating stages are able to both initiate and delay the lead and lag signals. 13. A ring time-to-digital converter system comprising: a. a Vernier ring comprising: i. a lead initiating stage for receiving a lead step signal and a lag initiating stage for receiving a lag step signal;ii. a plurality of serially coupled lead delay stages for enabling propagation of the lead step signal, wherein a last lead delay stage is coupled to an input of the lead initiating stage and a first lead delay stage is coupled to an output of the lead initiating stage thereby forming a lead ring; andiii. a plurality of serially coupled lag delay stages for enabling propagation of the lag step signal, wherein a last lag delay stage is coupled to an input of the lag initiating stage and a first lag delay stage is coupled to an output of the lag initiating stage thereby forming a lag ring, wherein each lead stage has a corresponding lag stage. 14. The converter system of claim 13 wherein the lead step signal propagates from the lead initiating stage along the lead ring and the lag step signal propagates from the lag initiating stage along the lag ring. 15. The converter system of claim 14 wherein each lead delay stage has an adjustable lead propagation delay interval that is greater than an adjustable lag propagation delay interval of each lag delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 16. The converter system of claim 15 further comprising a plurality of comparator pairs, wherein each pair is coupled to a lead output of a lead delay stage and a lag output of the corresponding lag delay stage. 17. The converter system of claim 16 wherein the plurality of comparator pairs each comprise an A-type comparator for detecting a lead or lag rising edge and a B-type comparator for detecting a lead or lag falling edge. 18. The converter system of claim 17 wherein outputs of the A-type comparators toggle between a logical one and a logical zero when the lag rising edge arrives before the lead rising edge, and outputs of the B-type comparators toggle between a logical one and a logical zero when the lag falling edge arrives before the lead falling edge. 19. The converter system of claim 15 further comprising a plurality of double-edge-triggered comparators, wherein each comparator is coupled to a lead output of a lead delay stage and a lag output of the corresponding lag delay stage. 20. The converter system of claim 19 wherein outputs of the comparators toggle between a logical one and a logical zero when either the lag rising edge arrives before the lead rising edge or the lag falling edge arrives before the lead falling edge. 21. The converter system of claim 20 further comprising pre-logic coupled to the lead and lag initiating stages for receiving a pair of input signals, determining which input signal arrived first, and outputting the signal that arrived first to the lead initiating stage as the lead signal and the signal that arrived second to the lag initiating stage as the lag signal. 22. The converter system of claim 21 wherein the pre-logic comprises a pre-logic comparator and a pair of multiplexers. 23. The converter system of claim 22 wherein the pre-logic is further coupled to an evaluation logic for outputting a sign bit to the evaluation logic. 24. The converter system of claim 23 further comprising control logic, wherein the control logic resets one of the comparators in each of the pairs of comparators every other time the lead step signal laps the lead ring. 25. The converter system of claim 24 further comprising a fine counter, wherein the fine counter is incremented each time the lead signal laps the lead ring. 26. The converter system of claim 25 further comprising a coarse counter, wherein the coarse counter is incremented each time the lead signal laps the lead ring before the lag signal arrives at the lag initiating stage. 27. The converter system of claim 26 further comprising a thermometer decoder coupled to outputs of the pairs of comparators for translating the output of the pairs of comparators from thermometer code to binary code. 28. The converter system of claim 27 wherein the evaluation logic is coupled to an output of the coarse counter, the fine counter, the thermometer decoder and the sign bit output by the pre-logic, for determining a time interval between the lead signal and the lag signal. 29. A method of measuring a time interval comprising: a. directing a lead signal to a lead initiating stage and a lag signal to a lag initiating stage, then outputting a sign bit;b. propagating the lead signal through a lead ring comprising a plurality of serially coupled lead delay stages;c. propagating the lag signal through a lag ring comprising a plurality of serially coupled lag delay stages, wherein each lead delay stage has a corresponding lag delay stage;d. determining a first number of laps through the lead ring the lead signal has propagated when the lag signal arrives at the lag initiating stage;e. determining at which lead delay stage and corresponding lag delay stage the lag signal passes the lead signal and recording a second number of laps around the lead ring the lead signal has propagated before the lead delay stage and corresponding lag delay stage; andf. calculating the time interval between the lead and lag signals. 30. The method of claim 29 further comprising receiving a pair of input signals and determining the lead signal and the lag signal, wherein the lead signal arrived before the lag signal. 31. The method of claim 29 wherein the last lead delay stage in the series is coupled to an input of the lead initiating stage and the first lead delay stage in the series is coupled to an output of the lead initiating stage thereby forming the lead ring and wherein the last lag delay stage in the series is coupled to an input of the lag initiating stage and the first lag delay stage in the series is coupled to an output of the lag initiating stage thereby forming the lag ring. 32. The method of claim 31 wherein each lead delay stage has an adjustable lead propagation delay interval that is greater than an adjustable lag propagation delay interval of each lag delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 33. The method of claim 29 wherein the determining at which lead and corresponding lag stage the lag signal passes the lead signal comprises determining an arrival sequence of the lead and lag signals at a plurality of pairs of comparators coupled to each lead stage and the corresponding lag stage. 34. The method of claim 33 further comprising control logic, wherein the control logic resets one of the comparators in each of the plurality of pairs of comparators every other time the lead step signal laps the lead ring. 35. The method of claim 31 wherein determining a first number of laps through the lead ring the lead signal has propagated when the lag signal arrives at the lag initiating stage further comprising incrementing a coarse counter each time the lead signal laps the lead ring. 36. The method of claim 31 wherein determining at which lead and corresponding lag stage the lag signal passes the lead signal and recording a second number of laps around the lead ring the lead signal had propagated before the lead delay stage and corresponding lag delay stage further comprises incrementing a fine counter each time the lead signal laps the lead ring. 37. The method of claim 33 further comprising translating an output of the pairs of comparators from thermometer code to binary code with a thermometer decoder. 38. The method of claim 37 further comprising disconnecting the lead ring and the lag ring after the lag signal passes the lead signal. 39. A time-to-digital converter comprising: a. a plurality of first delay lines comprising a plurality of serially coupled first delay stages;b. a plurality of second delay lines comprising a plurality of serially coupled second delay stages, wherein each first delay line has a corresponding second delay line;c. a plurality of comparators wherein each comparator is coupled to a first output of one of the first delay stages from one of the first delay lines and a second output of one of the second delay stages from the corresponding second delay lines thereby forming a plurality of matrixes; andd. a third delay line comprising a plurality of serially coupled third delay stages, wherein each of the third delay stages is coupled between inputs of the plurality of second delay lines and each of the matrixes. 40. The converter of claim 39 wherein the first delay stages are sequentially numbered along the first line and second delay stages are sequentially numbered along the second line. 41. The converter of claim 40 wherein each matrix comprises a plurality of comparator columns wherein a first column of the plurality of columns comprises a plurality of first comparators wherein each first comparator is coupled to the output of a first delay stage having a first number and the output of a second delay stage of an equal number, and further wherein a second column of the plurality of columns comprises a plurality of second comparators wherein each second comparator is coupled to the output of a first delay stage having a second number and the output of a second delay stage having a number that is greater than the second number by one. 42. The converter of claim 41 wherein an nth column of the plurality of columns comprises a plurality of nth comparators wherein each nth comparator is coupled to the output of a first delay stage having a third number and the output of a second delay stage having an nth number that is greater than the third number by (n−1). 43. The converter of claim 42 wherein the first delay stages have an adjustable first delay interval, the second delay stages have an adjustable second delay interval and the third delay stages have an adjustable third delay interval, and further wherein the first delay interval is less than the second delay interval which is less than the third delay interval. 44. The converter of claim 43 wherein the third delay interval is equal to the second delay interval multiplied by the number of second delay stages in one of the plurality of second delay lines minus the first delay interval multiplied by the number of first delay stages in one of the plurality of first delay lines. 45. The converter of claim 44 wherein the second delay interval is equal to the difference between the first and second delay intervals multiplied by the number of first delay stages in one of the plurality of first delay lines. 46. The converter of claim 45 wherein the third delay line and the initial one of the second delay lines are configured to receive a lead signal, and the first delay lines are configured to receive a lag signal, wherein the lead signal is ahead of the lag signal. 47. The converter of claim 46 wherein the remainder of the second delay lines are configured to receive the lead signal as the lead signal propagates through each third stage of the third delay line. 48. A time-to-digital converter comprising: a. a lead initiating stage for receiving a lead step signal and a lag initiating stage for receiving a lag step signal;b. a plurality of serially coupled lead delay stages, wherein a last lead delay stage is coupled to an input of the lead initiating stage and a first lead delay stage is coupled to an output of the lead initiating stage thereby forming a lead ring; andc. a plurality of serially coupled lag delay stages, wherein a last lag delay stage is coupled to an input of the lag initiating stage and a first lag delay stage is coupled to an output of the lag initiating stage thereby forming a lag ring;d. a plurality of comparators wherein each comparator is coupled to a lag output of one of the lag delay stages and a lead output of one of the lead delay stages thereby forming a matrix; ande. a lap counter configured to count the number of laps that the lead signal has propagated through the lead ring before the lag signal passes the lead signal and before the lag signal arrives at the lag initiating stage. 49. The converter of claim 48 wherein the initiating stages comprise any combination of NAND gates, multiplexers, multi-switches or any other type of logic gate able to initiate the propagation of signals. 50. The converter of claim 48 wherein the delay stages comprise any combination of single-ended or differential inverters, buffers or any other type of logic gate able to delay and/or toggle the propagating signals. 51. The converter of claim 48 wherein the comparators comprise any combination of single-ended or differential arbiters, flip flops, latches or any other type of comparator. 52. The converter of claim 48 wherein the lag delay stages are sequentially numbered along the lag ring and lead delay stages are sequentially numbered along the lead ring. 53. The converter of claim 52 wherein the matrix comprises a plurality of comparator columns wherein a first column of the plurality of columns comprises a plurality of first comparators wherein each first comparator is coupled to the output of a lag delay stage having a first number and the output of a lead delay stage of an equal number, and further wherein a second column of the plurality of columns comprises a plurality of second comarators wherein each second comparator is coupled to the output of a lag delay stage having a second number and the output of a lead delay stage having a number that is greater than the second number by one. 54. The converter of claim 53 wherein an nth column of the plurality of columns comprises a plurality of nth comparators wherein each nth comparator is coupled to the output of a lag delay stage having a third number and the output of a lead delay stage having an nth number that is greater than the third number by (n−1). 55. The converter of claim 54 wherein each lead delay stage has an adjustable lead propagation delay interval that is greater than an adjustable lag propagation delay interval of each lag delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 56. The converter of claim 55 wherein the lead propagation delay interval is equal to the difference between the lead and lag propagation delay intervals multiplied by the number of lag delay stages in the lag delay ring. 57. The converter of claim 56 wherein the lead initiating stage comprises one of the lead delay stages and the lag initiating stage comprises one of the lag delay stages such that the lead and lag initiating stages are able to both initiate and delay the lead and lag signals. 58. The converter of claim 57 wherein the comparators are grouped in order to form a plurality of comparator pairs, and further wherein both comparators in each comparator pair are coupled to the same lag output of one of the lag delay stages and the same lead output of one of the lead delay stages thereby forming the matrix. 59. The converter of claim 58 wherein the plurality of comparator pairs each comprise an A-type comparator for detecting the lead or lag rising edge and a B-type comparator for detecting the lead or lag falling edge. 60. The converter of claim 59 wherein outputs of the A-type comparators toggle between a logical one and a logical zero when the lag rising edge arrives before the lead rising edge, and outputs of the B-type comparators toggle between a logical one and a logical zero when the lag falling edge arrives before the lead falling edge. 61. The converter of claim 57 further comprising a second lap counter, wherein the second lap counter is configured to count the number of laps that the lag signal has propagated through the lag ring before the lag signal passes the lead signal. 62. The converter of claim 57 further comprising a plurality of double-edge-triggered comparators, wherein each comparator is coupled to a lead output of a lead delay stage and a lag output of the corresponding lag delay stage. 63. The converter of claim 62 wherein outputs of the comparators toggle between a logical one and a logical zero when either the lag rising edge arrives before the lead rising edge or the lag falling edge arrives before the lead falling edge. 64. An n-dimensional time-to-digital converter with comparator matrixes comprising: a. a first delay line of an nth dimension comprising a plurality of serially coupled first delay stages;b. a second delay line of the nth dimension comprising a plurality of serially coupled second delay stages; andc. a plurality of n−1 dimensional time-to-digital converters with comparator matrixes each having a lead signal input and a lag signal input; wherein the lead signal inputs are coupled to the second delay line such that one lead signal input is coupled before and after each second delay stage, and further wherein the lag signal inputs are coupled to the first delay line such that one lag signal input is coupled before and after each first delay stage. 65. The converter of claim 64 wherein the first delay stages have an adjustable first delay interval, the second delay stages have an adjustable second delay interval, and further wherein the first delay interval is less than the second delay interval. 66. The converter of claim 65 wherein the n−1 dimensional converters further comprise an n−1 delay interval, wherein the n−1 delay interval is equal to the difference between the first interval and the second interval. 67. An n-dimensional ring time-to-digital converter with a comparator matrix comprising: a. a lead initiating stage of an nth dimension for receiving a lead step signal and a lag initiating stage of the nth dimension for receiving a lag step signal;b. a plurality of serially coupled lead delay stages of the nth dimension, wherein a last lead delay stage is coupled to an input of the lead initiating stage and a first lead delay stage is coupled to an output of the lead initiating stage thereby forming a lead ring; andc. a plurality of serially coupled lag delay stages of the nth dimension, wherein a last lag delay stage is coupled to an input of the lag initiating stage and a first lag delay stage is coupled to an output of the lag initiating stage thereby forming a lag ring;d. a lap counter of an nth dimension configured to count a number of laps that the lead step signal has propagated through the lead ring before the lag signal passes the lead signal and before the lag signal arrives at the lag initiating stage; ande. a plurality of n−1 dimensional ring time-to-digital converters with a comparator matrix each having a lead signal input and a lag signal input; wherein the lead signal inputs are coupled to the lead delay line such that one lead signal input is coupled before and after each lead delay stage, and further wherein the lag signal inputs are coupled to the lag delay line such that one lag signal input is coupled before and after each lag delay stage. 68. The converter of claim 67 wherein the lag delay stages have an adjustable lag delay interval, the lead delay stages have an adjustable lead delay interval, and further wherein the lag delay interval is less than the lead delay interval. 69. The converter of claim 68 wherein the n−1 dimensional ring time-to-digital converters with a comparator matrix further comprise an n−1 delay interval, wherein the n−1 delay interval is equal to the difference between the lag interval and the lead interval. 70. A method of measuring a time interval comprising: a. directing a lead signal to a lead initiating stage of the nth dimension and a lag signal to a lag initiating stage of the nth dimension, then outputting a sign bit of the nth dimension;b. propagating the lead signal through a lead ring of the nth dimension comprising a plurality of serially coupled lead delay stages;c. propagating the lag signal through a lag ring of the nth dimension comprising a plurality of serially coupled lag delay stages, wherein each lead delay stage has a corresponding lag delay stage;d. determining a first number of laps through the lead ring the lead signal has propagated when the lag signal arrives at the lag initiating stage;e. determining at which lead and corresponding lag delay stage the lag signal passes the lead signal and recording a second number of laps around the lead ring the lead signal has propagated before the lead delay stage and corresponding lag delay stage;f. calculating a n−1 time interval between the lead and lag signals;g. calculating a n time interval between the lead and lag signals; andh. adding the n−1 time interval and the n time interval. 71. The method of claim 70 wherein the last lead delay stage in the series is coupled to an input of the lead initiating stage and the first lead delay stage in the series is coupled to an output of the lead initiating stage thereby forming the lead ring and wherein the last lag delay stage in the series is coupled to an input of the lag initiating stage and the first lag delay stage in the series is coupled to an output of the lag initiating stage thereby forming the lag ring. 72. The method of claim 71 wherein each lead delay stage has an adjustable lead propagation delay interval that is greater than an adjustable lag propagation delay interval of each lag delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 73. The method of claim 70 wherein determining a first number of laps through the lead ring the lead signal has propagated when the lag signal arrives at the lag initiating stage further comprises incrementing a coarse counter each time the lead signal laps the lead ring. 74. The method of claim 70 wherein determining at which lead and corresponding lag stage the lag signal passes the lead signal and recording a second number of laps around the lead ring the lead signal had propagated before the lead delay stage and corresponding lag delay stage further comprises incrementing a fine counter each time the lead signal laps the lead ring. 75. The method of claim 70 further comprising disconnecting the lead ring and the lag ring after the lag signal passes the lead signal. 76. A method of measuring a time interval comprising: a. propagating the lag signal through a first delay line of the nth dimension comprising a plurality of serially coupled first delay stages;b. propagating the lead signal through a second delay line of the nth dimension comprising a plurality of serially coupled second delay stages, wherein each first delay stage has a corresponding second delay stage;c. propagating the lead and lag signal through a plurality of n−1 dimensional matrix time-to-digital converters each having a lead signal input and a lag signal input;d. determining at which first and corresponding second delay stage the lag signal passes the lead signal;e. calculating a n−1 time interval between the lead and lag signals;f. calculating a n time interval between the lead and lag signals; andg. adding the n−1 time interval and the n time interval. wherein the lead signal inputs are coupled to the second delay line such that one lead signal input is coupled before and after each second delay stage, and further wherein the lag signal inputs are coupled to the first delay line such that one lag signal input is coupled before and after each first delay stage. 77. The method of claim 76 wherein each first delay stage has an adjustable first propagation delay interval that is less than an adjustable second propagation delay interval of each second delay stage such that after each stage a lag rising and lag falling edge of the lag signal begins to catch up with a lead rising and lead falling edge of the lead signal. 78. A method of measuring a time interval comprising: a. directing a lead signal to a lead initiating stage and a lag signal to a lag initiating stage, then outputting a sign bit;b. propagating the lead signal through a lead ring comprising a plurality of serially coupled lead delay stages;c. propagating the lag signal through a lag ring comprising a plurality of serially coupled lag delay stages, wherein each lead delay stage has a corresponding lag delay stage;d. detecting at which lap of propagation the lag signal passes the lead signal;e. determining a number of laps through the lead ring the lead signal has propagated and a number of laps through the lag ring the lag signal has propagated before the lag signal has passed the lead signal;f. disconnecting the lead ring and lag ring before a next lap starts after at least one converter detects that the lag signal has passed the lead signal;g. determining at which lead delay stage and corresponding lag delay stage the lag signal passes the lead signal by comparing results of a comparator matrix;h. calculating the time interval between lead signal and lag; andi. restoring calculation results and resetting the system to be ready for the next measuring cycle. 79. The method of claim 78 further comprising control logic, wherein the control logic resets one of the comparators in each of the plurality of pairs of comparators every other time the lead step signal laps the lead ring.