초록 ▼

A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the firs

A time to digital converter includes: a first measurement unit measuring a time difference between a start signal and a stop signal as a first time unit by using a first delay line; a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line as a second time unit by using a second delay line and a third delay line and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; and an output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit.

대표청구항 ▼

1. A time to digital converter comprising: a first measurement unit measuring a time difference between a start signal and a stop signal by a first time unit by using a first delay line;a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the

1. A time to digital converter comprising: a first measurement unit measuring a time difference between a start signal and a stop signal by a first time unit by using a first delay line;a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line by a second time unit by using a second delay line and a third delay line, and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; andan output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit,wherein the output unit comprises a calculation unit subtracting a time difference between a stop signal measured by the second measurement unit and a start signal delayed by a first delay line from a time difference between a start signal and a stop signal measured by the first measurement unit to calculate the final time difference. 2. A time to digital converter comprising: a first measurement unit measuring a time difference between a start signal and a stop signal by a first time unit by using a first delay line;a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line by a second time unit by using a second delay line and a third delay line, and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; andan output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit,wherein the first measurement unit comprises:a first delay line receiving the start signal and including a plurality of cascaded delay cells delaying an input signal by the first time unit;a plurality of time comparators outputting a digital signal by comparing an application time of the start signal delayed by the delay cell of the first delay line with an application time of the stop signal; anda multiplexer selecting one of the start signals delayed by the plurality of delay cells according to a digital signal outputted from at least one of the plurality of time comparators. 3. The converter of claim 2, wherein at least one of the plurality of time comparators outputs a digital signal having a logic level of 1 when the start signal delayed by the delay cell is received before the stop signal, and outputs a digital signal having a logic level of 0 when the start signal delayed by the delay cell is received after the stop signal. 4. The converter of claim 3, wherein at least one of the plurality of time comparators is a D flip-flop receiving the start signal delayed by the delay cell as data and receiving the stop signal as a clock. 5. The converter of claim 3, wherein the multiplexer selects a signal applied first from delayed start signals received by a time comparator outputting a digital signal having a logic level of 0, and then provides the selected signal to the second measurement unit. 6. The converter of claim 5, wherein the multiplexer comprises a plurality of AND gates receiving an output signal of a delay cell, an inverted signal of an output signal of a time comparator receiving an output signal of a corresponding delay cell, and an output signal of a previous time comparator disposed at a front end of a corresponding time comparator and performing an AND operation on the received signals. 7. A time to digital converter comprising: a first measurement unit measuring a time difference between a start signal and a stop signal by a first time unit by using a first delay line;a second measurement unit measuring a time difference between the stop signal and the start signal delayed by the first delay line by a second time unit by using a second delay line and a third delay line, and comparing an output signal of one delay cell included in the second delay line with an output signal of at least two delay cells included in the third delay line; andan output unit outputting a final time difference between the start signal and the stop signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit,wherein the second measurement unit comprises:a second delay line receiving the start signal delayed by the first delay line and including a plurality of cascaded delay cells delaying an input signal by a second delay time;a third delay line receiving the stop signal and including a plurality of cascaded delay cells delaying an input signal by a third delay time; anda plurality of time comparators outputting a digital signal by comparing an application time of a start signal delayed by a delay cell of the second delay line with an application time of a stop signal delayed by a delay cell of the third delay line. 8. The converter of claim 7, wherein the second time unit is a time difference between the third delay time and the second delay time. 9. The converter of claim 1, wherein the first time unit is greater than the second time unit. 10. The converter of claim 7, wherein the plurality of time comparators are configured to compare one delayed start signal outputted from the second delay line with a plurality of delayed stop signals outputted from the third delay line. 11. The converter of claim 7, wherein at least one of the plurality of time comparators outputs a digital signal having a logic level of 1 when the stop signal delayed by the delay cell of the third delay line is received before the start signal delayed by the delay cell of the second delay line, and outputs a digital signal having a logic level of 0 when the stop signal delayed by the delay cell of the third delay line is received after the start signal delayed by the delay cell of the second delay line. 12. The converter of claim 11, wherein at least one of the plurality of time comparators is a D flip-flop receiving the stop signal delayed by the delay cell of the third delay line as data and receiving the start signal delayed by the delay cell of the second delay line as a clock. 13. The converter of claim 2, wherein the delay cell comprises: a first sub delay cell delaying the start signal by a portion of the first time unit; anda second sub delay cell delaying a start signal delayed by the first sub delay cell by the remaining of the first time unit. 14. The converter of claim 13, wherein the multiplexer comprises a plurality of AND gates receiving an output signal of a first sub delay cell, an inverted signal of an output signal of a time comparator receiving a start signal inputted to a corresponding first sub delay cell, and an output signal of a previous time comparator disposed at a front end of a corresponding time comparator and performing an AND operation on the received signals. 15. A time to digital converter comprises: a first delay line including a plurality of cascaded first delay cells, receiving a start signal, and delaying the start signal by a first delay time and outputting the delayed signal each time the start signal passes through the first delay cell;a plurality of first time comparators receiving an output signal and a stop signal of the first delay, and comparing application times of the two signals;a multiplexer selecting a signal whose application time is later than that of the stop signal and having the smallest time difference with the stop signal from output signals of the plurality of first delay cells by using an output signal of the first time comparator;a second delay line including a plurality of cascaded second delay cells, receiving the signal selected by the multiplexer, and delaying the signal selected by the multiplexer by a second delay time and outputting the delayed signal each time the signal selected by the multiplexer passes through the second delay cell;a third delay line including a plurality of cascaded third delay cells, receiving the stop signal, and delaying the stop signal by a third delay time and outputting the delayed signal each time the stop signal passes through the third delay cell; anda plurality of second time comparators receiving an output signal of the second delay cell and an output signal of the third delay cell, and comparing application times of the two signals,wherein an output signal of one second delay cell included in the second delay line is compared with an output signal of at least two third delay cells included in the third delay line. 16. The converter of claim 15, wherein at least one of the plurality of first time comparators is a D flip-flop receiving an output signal of the first delay cell as data and receives the stop signal as a clock; outputting a digital signal having a logic level of 1 when the output signal of the first delay cell is received before the stop signal; and outputting a digital signal having a logic level of 0 when the output signal of the first delay cell is received after the stop signal. 17. The converter of claim 15, wherein the multiplexer comprises a plurality of AND gates receiving an output signal of a first delay cell, an inverted signal of an output signal of a first time comparator receiving an output signal of a corresponding first delay cell, and an output signal of a previous first time comparator disposed at a front end of a corresponding first time comparator and performing an AND operation on the received signals. 18. The converter of claim 15, wherein at least one of the plurality of second time comparators is a D flip-flop receiving an output signal of the third delay cell as data and receiving an output signal of the second delay cell as a clock; outputting a digital signal having a logic level of 1 when the output signal of the third delay cell is received before the output signal of the second delay cell; and outputting a digital signal having a logic level of 0 when the output signal of the third delay cell is received after the output signal of the second delay cell. 19. The converter of claim 15, wherein the first delay cell comprises: a first sub delay cell delaying the start signal by half of the first delay time; anda second sub delay cell further delaying the start signal delayed by the first sub delay cell by half of the first delay time. 20. The converter of claim 19, wherein the multiplexer comprises a plurality of AND gates receiving an output signal of a first sub delay cell, an inverted signal of an output signal of a first time comparator receiving a start signal inputted to a corresponding first sub delay cell, and an output signal of a previous first time comparator disposed at a front end of a corresponding first time comparator and performing an AND operation on the received signals. 21. The converter of claim 15, further comprising an output unit outputting a time difference between the start signal and the stop signal as a digital code on the basis of output signals of at least one of the plurality of the first time comparators and the second time comparators. 22. The converter of claim 21, wherein the output unit comprises an encoder converting a thermometer code into a binary code. 23. A time to digital converter comprising: a clock count measurement unit measuring the number of clocks between a start signal and a stop signal;an interface unit outputting a delay signal by delaying the stop signal;a conversion unit measuring a time difference between the stop signal and the delay signal, and converting the measured time difference into a digital code; andan output logic unit outputting the time difference between the start signal and the stop signal as a digital code on the basis of the number of counts and the time difference,wherein the conversion unit comprises:a first measurement unit measuring the time difference between the start signal and the stop signal by a first time unit by using a first delay line;a second measurement unit measuring a time difference between the delay signal and a stop signal delayed by the first delay line by a second time unit by using a second delay line and a third delay line, wherein one delay cell included in the second delay line matches at least two delay cells included in the third delay line; andan output unit outputting a final time difference between the stop signal and the delay signal as a digital code on the basis of measurement results of the first measurement unit and the second measurement unit. 24. The converter of claim 23, wherein the clock count measurement unit comprises: an AND gate generating an enable signal by performing an AND operation on the start signal and an inverted signal of the stop signal; anda counter receiving the enable signal and the clock signal and counting the number of clocks inputted while the enable signal is applied. 25. The converter of claim 23, wherein the interface unit comprises a first D flip-flop receiving the stop signal as data and receiving a clock signal as a clock and a second D flip-flop receiving an output signal of the first D flip-flop as data and receiving the clock signal as a clock to output the delay signal. 26. The converter of claim 23, wherein the output logic unit adds a bit corresponding to the number of D flip-flops included in the interface unit to a bit corresponding to the number of clocks and subtracts a bit corresponding to a time difference between the stop signal and the delay signal.