An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tan
An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, includes an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node and a LC-tank structure coupled between the VDD power rail node and the VSS power rail node and to the RF I/O pad. The LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad. At least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes.
대표청구항▼
1. An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, the ESD circuit comprising: an ESD clamp circuit coupled between a VDD power rail node and the VSS power
1. An electrostatic discharge (ESD) circuit, adaptive to a radio frequency (RF) device, which includes a RF circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad, the ESD circuit comprising: an ESD clamp circuit coupled between a VDD power rail node and the VSS power rail node; anda LC-tank structure coupled between the VDD power rail and the VSS power rail nodes and to the RF I/O pad, wherein the LC-tank structure includes a first ESD block between the VDD power rail node and the RF I/O pad, and a second ESD block between the VSS power rail node and the RF I/O pad,wherein at least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes. 2. The ESD circuit of claim 1, wherein the first ESD block includes the pair of diodes coupled in parallel with each other and the inductor coupled in series with one of the pair of diodes, andwherein the second ESD block includes a single diode coupled between the RF I/O pad and the VSS power rail node. 3. The ESD circuit of claim 2, wherein the inductor is adapted to compensate for parasitic capacitance induced at the I/O pad by the LC-tank structure. 4. The ESD circuit of claim 2, wherein the one of the pair of diodes has a cathode coupled to the VDD power rail node and an anode coupled to the inductor. 5. The ESD circuit of claim 2, wherein the one of the pair of diodes has an anode coupled to the I/O pad and a cathode coupled to the inductor. 6. The ESD circuit of claim 1, wherein the second ESD block includes the pair of diodes coupled in parallel with each other and the inductor coupled in series with one of the pair of diodes, andwherein the first ESD block includes a single diode coupled between the RF I/O pad and the VSS power rail node. 7. The ESD circuit of claim 6, wherein the inductor is adapted to compensate for parasitic capacitance induced at the I/O pad by the LC-tank structure. 8. The ESD circuit of claim 6, wherein the one of the pair of diodes has a cathode coupled to the inductor and an anode coupled to the VSS power rail node. 9. The ESD circuit of claim 6, wherein the one of the pair of diodes has an anode coupled to inductor and a cathode coupled to the I/O pad. 10. The ESD circuit of claim 1, wherein both the first and second ESD blocks each include a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes. 11. The ESD circuit of claim 10, wherein the inductor of the first ESD block and the inductor of the second ESD block are adapted to compensate for parasitic capacitance induced at the I/O pad by the first and second ESD blocks, respectively. 12. The ESD circuit of claim 1, wherein the other of the pair of diodes has a parasitic capacitance forming a capacitor portion of an LC circuit with the inductor. 13. A radio frequency (RF) device comprising: a circuit coupled between a VDD power rail and a VSS power rail and having a RF I/O pad;an ESD clamp circuit coupled between the VDD power rail and the VSS power rail; anda LC-tank structure coupled between the VDD power rail and the VSS power rail and between the RF I/O pad and the RF circuit, wherein the LC-tank structure includes a first ESD block between the VDD power rail and the RF I/O pad, and a second ESD block between the VSS power rail and the RF I/O pad,wherein at least one of the first and second ESD blocks includes a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes. 14. The ESD circuit of claim 13, wherein the other of the pair of diodes has a parasitic capacitance forming a capacitor portion of an LC circuit with the inductor. 15. The ESD circuit of claim 13, wherein the first ESD block includes the pair of diodes coupled in parallel with each other and the inductor coupled in series with one of the pair of diodes, andwherein the second ESD block includes a single diode coupled between the RF I/O pad and the VSS power rail. 16. The ESD circuit of claim 15, wherein the inductor is adapted to compensate for parasitic capacitance induced at the I/O pad by the LC-tank structure. 17. The ESD circuit of claim 13, wherein the second ESD block includes the pair of diodes coupled in parallel with each other and the inductor coupled in series with one of the pair of diodes, andwherein the first ESD block includes a single diode coupled between the RF I/O pad and the VSS power rail. 18. The ESD circuit of claim 17, wherein the inductor is adapted to compensate for parasitic capacitance induced at the I/O pad by the LC-tank structure. 19. The ESD circuit of claim 13, wherein both the first and second ESD blocks each include a pair of diodes coupled in parallel with each other and an inductor coupled in series with one of the pair of diodes. 20. The ESD circuit of claim 19, wherein the inductor of the first ESD block and the inductor of the second ESD block are adapted to compensate for parasitic capacitance induced at the I/O pad by the first and second ESD blocks, respectively.
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