IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0238816
(2011-09-21)
|
등록번호 |
US-8493813
(2013-07-23)
|
우선권정보 |
KR-10-2010-0110795 (2010-11-09) |
발명자
/ 주소 |
|
출원인 / 주소 |
- Samsung Electronics Co., Ltd.
|
대리인 / 주소 |
F. Chau & Associates, LLC
|
인용정보 |
피인용 횟수 :
2 인용 특허 :
2 |
초록
▼
A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second
A row decoder circuit includes a decoding unit and first and second wordline driving units. The decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages. A voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode. The first wordline driving unit is connected to a first wordline and outputs one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals. The second wordline driving unit is connected to a second wordline and outputs one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals.
대표청구항
▼
1. A row decoder circuit, comprising: a decoding unit configured to generate a first driving signal and a second driving signal based on a selection signal and wordline voltages, wherein a voltage level of the first driving signal and a voltage level of the second driving signal depend on an operati
1. A row decoder circuit, comprising: a decoding unit configured to generate a first driving signal and a second driving signal based on a selection signal and wordline voltages, wherein a voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode;a first wordline driving unit connected to a first wordline and configured to output one of the first driving signal and the second driving signal as a first wordline driving signal based on first driving control signals; anda second wordline driving unit connected to a second wordline and configured to output one of the first driving signal and the second driving signal as a second wordline driving signal based on second driving control signals,wherein the first driving control signals each have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the first wordline is selected, and the second driving control signals each have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the second wordline is selected. 2. The row decoder circuit of claim 1, wherein the first wordline driving unit includes: a first p-type metal oxide semiconductor (PMOS) transistor having a first electrode connected to the first wordline, a gate electrode receiving a first control signal of the first driving control signals, and a second electrode receiving the first driving signal; anda second PMOS transistor having a first electrode receiving the second driving signal, a gate electrode receiving a second control signal of the first driving control signals, and a second electrode connected to the first electrode of the first PMOS transistor,wherein the second wordline driving unit includes:a third PMOS transistor having a first electrode connected to the second wordline, a gate electrode receiving a first control signal of the second driving control signals, and a second electrode receiving the first driving signal; anda fourth PMOS transistor having a first electrode receiving the second driving signal, a gate electrode receiving a second control signal of the second driving control signals, and a second electrode connected to the first electrode of the third PMOS transistor. 3. The row decoder circuit of claim 2, wherein the first control signal of the first or second driving control signals has one of a first voltage level and a second voltage level, and the second control signal of the first or second driving control signals has the other the of the first voltage level and the second voltage level, wherein the first voltage level is lower than the voltage level of the first driving signal and the second voltage level is about the same as the voltage level of the second driving signal. 4. The row decoder circuit of claim 1, wherein the operation mode includes a program mode, the first driving control signals include a first and a second control signal, and the second driving control signals include a first and a second control signal, and wherein the first wordline driving unit outputs the first driving signal as the first wordline driving signal in response to the first control signal of the first driving control signals having a program control voltage level when the first wordline is not selected in the program mode, and the second wordline driving unit outputs the first driving signal as the second wordline driving signal in response to the first control signal of the second driving control signals having the program control voltage level when the second wordline is not selected in the program mode, wherein the program control voltage level is lower than the voltage level of the first driving signal. 5. The row decoder circuit of claim 4, wherein the first wordline driving unit outputs the second driving signal as the first wordline driving signal in response to the second control signal of the first driving control signals having the program control voltage level when the first wordline is selected in the program mode, and the second wordline driving unit outputs the second driving signal as the second wordline driving signal in response to the second control signal of the second driving control signals having the program control voltage level when the second wordline is selected in the program mode. 6. The row decoder circuit of claim 5, wherein the second driving signal has a first program voltage level and the first driving signal has a second program voltage level in the program mode. 7. The row decoder circuit of claim 6, wherein the first control signal of the first driving control signals has the first program voltage level when the first wordline is selected in the program mode, the second control signal of the first driving control signals has the first program voltage level when the first wordline is not selected in the program mode, the first control signal of the second driving control signals has the first program voltage level when the second wordline is selected in the program mode, and the second control signal of the second driving control signals has the first program voltage level when the second wordline is not selected in the program mode. 8. The row decoder circuit of claim 1, wherein the operation mode includes an erase mode, the first driving control signals include a first and a second control signal, and the second driving control signals include a first and second control signal, and wherein the first wordline driving unit outputs the first driving signal as the first wordline driving signal in response to the first control signal of the first driving control signals having an erase control voltage level when the first wordline is selected in the erase mode, and the second wordline driving unit outputs the first driving signal as the second wordline driving signal in response to the first control signal of the second driving control signals having the erase control voltage level when the second wordline is selected in the erase mode, wherein the erase control voltage level is lower than the voltage level of the first driving signal. 9. The row decoder circuit of claim 8, wherein the first wordline driving unit outputs the second driving signal as the first wordline driving signal in response to the second control signal of the first driving control signals having the erase control voltage level when the first wordline is not selected in the erase mode, and the second wordline driving unit outputs the second driving signal as the second wordline driving signal in response to the second control signal of the second driving control signals having the erase control voltage level when the second wordline is not selected in the erase mode. 10. The row decoder circuit of claim 9, wherein the first driving signal has a first erase voltage level and the second driving signal has a second erase voltage level in the erase mode. 11. The row decoder circuit of claim 10, wherein the first control signal of the first driving control signals has the second erase voltage level when the first wordline is not selected in the erase mode, the second control signal of the first driving control signals has the second erase voltage level when the first wordline is selected in the erase mode, the first control signal of the second driving control signals has the second erase voltage level when the second wordline is not selected in the erase mode, and the second control signal of the second driving control signals has the second erase voltage level when the second wordline is selected in the erase mode. 12. The row decoder circuit of claim 1, wherein the decoding unit includes: a first n-type metal oxide semiconductor (NMOS) transistor having a first electrode connected to a first node outputting the second driving signal, a gate electrode receiving the selection signal, and a second electrode connected to a ground voltage;a second NMOS transistor having a first electrode connected to a second node outputting the first driving signal, a gate electrode receiving an inversion signal of the selection signal, and a second electrode connected to the ground voltage; anda latch unit connected between a first wordline voltage and a second wordline voltage, and connected to the first node and the second node. 13. The row decoder circuit of claim 1, wherein all transistors of the first and second wordline driving units are of the same type. 14. A row decoder circuit, comprising: a global decoder configured to select one of global wordlines based on an address signal and configured to generate selection signals corresponding to the global wordlines;first and second local decoders, wherein the first local decoder is connected to a first global wordline and configured to provide first wordline driving signals to first local wordlines based on a first selection signal, wordline voltages and a first set of driving control signals, the second local decoder is connected to a second global wordline and configured to provide second wordline driving signals to second local wordlines based on a second selection signal, the wordline voltages and a second set of driving control signals, and the first local decoder comprises:a decoding unit configured to generate a first driving signal and a second driving signal based on the first selection signal and the wordline voltages, wherein a voltage level of the first driving signal and a voltage level of the second driving signal depend on an operation mode;a first wordline driving unit connected to a first of the first local wordlines and configured to output one of the first driving signal and the second driving signal as a first of the first wordline driving signals based on first driving control signals of the first set of driving control signals; anda second wordline driving unit connected to a second of the first local wordlines and configured to output one of the first driving signal and the second driving signal as a second of the first wordline driving signals based on second driving signals of the first set of driving control signals,wherein the first driving control signals of the first set of driving control signals have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the first of the first local wordlines is selected, and the second driving control signals of the first set of driving control signals have a voltage level that is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether the second of the first local wordlines is selected. 15. The row decoder circuit of claim 14, wherein the operation mode includes a program mode, and wherein the second driving signal has a first program voltage level when the first global wordline is selected in the program mode and has a second program voltage level when the first global wordline is not selected in the program mode, and the first driving signal has the second program voltage level in the program mode. 16. The row decoder circuit of claim 14, wherein the operation mode includes an erase mode, and wherein the first driving signal has a first erase voltage level when the first global wordline is selected in the erase mode and has a second erase voltage level when the first global wordline is not selected in the erase mode, and the second driving signal has the second erase voltage level in the erase mode. 17. The row decoder circuit of claim 14, wherein all transistors of the first and second wordline driving units are of the same type. 18. A row decoder, comprising: a decoding unit; andfirst and second word line driving units,wherein the decoding unit generates a first driving signal and a second driving signal based on a selection signal and wordline voltages, the first wordline driving unit outputs one of the first and second driving signals as a first wordline driving signal based on first driving control signals, the second wordline driving unit outputs one of the first and second driving signals as a second wordline driving signal based on second driving control signals, and all transistors of the first and second wordline driving units are of the same type,wherein a voltage level of each of the first driving control signals is lower than a voltage level of the first driving signal or is about the same as a voltage level of the second driving signal depending on whether a first wordline is selected, and a voltage level of each of the second driving control signals is lower than the voltage level of the first driving signal or is about the same as the voltage level of the second driving signal depending on whether a second wordline is selected. 19. The row decoder of claim 18, wherein a voltage level of the first driving signal and a voltage level of the second driving signal are determined according to an operating mode of a semiconductor device.
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