A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to
A method includes thinning a first region of an active layer, for form a stepped surface in the active layer defined by the first region and a second region of the active layer, depositing an planarizing layer on the active layer that defines a planar surface disposed on the active layer, etching to define nanowires and pads in the first region of the active layer, suspending the nanowires over the BOX layer, etching fins in the second region of the active layer forming a first gate stack that surrounds portion of each of the nanowires, forming a second gate stack covering a portion of the fins, and growing an epitaxial material wherein the epitaxial material defines source and drain regions of the nanowire FET and source and drain regions of the finFET.
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1. A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit having a nanowire field-effect transistor (FET) and a finFET, the method comprising: providing a wafer having an active layer over a buried oxide (BOX), wherein the active layer includes at least a first region and a
1. A method of fabricating a complementary metal-oxide semiconductor (CMOS) circuit having a nanowire field-effect transistor (FET) and a finFET, the method comprising: providing a wafer having an active layer over a buried oxide (BOX), wherein the active layer includes at least a first region and a second region;thinning the first region of the active layer, for forming a stepped surface in the active layer defined by the first region and the second region of the active layer;depositing an organic planarizing layer on the active layer that defines a planar surface disposed on the active layer;forming a first lithography hardmask on the organic planarizing layer over portions of the first region of the active layer and a second lithography hardmask on the organic planarizing layer over portions of the second region of the active layer;etching to define nanowires and pads in the first region of the active layer;suspending the nanowires over the BOX layer;etching fins in the second region of the active layer using the second lithography hardmask;forming a first gate stack that surrounds at least a portion of each of the nanowires, wherein the portions of each of the nanowires surrounded by the first gate stack define a channel region of a nanowire FET;forming a second gate stack covering at least a portion of each of the fins, wherein the portions of the fins covered by the second gate stack define a channel region of the finFET; andsimultaneously growing an epitaxial material on exposed portions of the nanowires, the pads and the fins, wherein the epitaxial material grown on the exposed portions of the nanowires and the pads define source and drain regions of the nanowire FET and wherein the epitaxial material grown on the exposed portions of the fins defines source and drain regions of the finFET. 2. The method of claim 1, further comprising forming a hardmask on the second region of the active layer prior to thinning the first region of the active layer. 3. The method of claim 2, wherein forming the hardmask comprises: depositing a hardmask material onto the active layer; andremoving a portion of the hardmask material from the first region of the active layer to expose the first region of the active layer. 4. The method of claim 1, further comprising depositing a resist that covers and protects the nanowires prior to etching the fins in the second region of the active layer. 5. The method of claim 1, wherein the fins are partially etched in the second region of the active layer during the etching of the nanowires and the pads in the first region of the active layer. 6. The method of claim 1, further comprising forming spacers on opposing sides of the first gate stack and on opposing sides of the second gate stack. 7. The method of claim 1, wherein the active layer comprises a semiconducting material selected from a group consisting of: silicon, germanium and silicon germanium. 8. The method of claim 1, wherein the first region of the active layer is thinned using a timed reactive ion etching process. 9. The method of claim 1, wherein the organic planarizing layer is deposited on the active layer using a spin coating process. 10. The method of claim 1, wherein the nanowires are suspended over the BOX layer by removing portions of the BOX layer beneath the nanowires. 11. The method of claim 10, wherein the BOX layer beneath the nanowires is removed using an isotropic etching process. 12. The method of claim 1, further comprising annealing the nanowires to smoothen the nanowires. 13. The method of claim 12, wherein the annealing is performed at a temperature of approximately 600° C. to approximately 1,000° C. in an atmosphere containing hydrogen. 14. The method of claim 1, wherein the forming the first gate stack comprises: depositing a conformal gate dielectric film around the nanowires;depositing a conformal metal gate film over the conformal gate dielectric film;depositing polysilicon over the conformal metal gate film; andpatterning the polysilicon, the conformal gate dielectric film and the conformal metal gate film to form the first gate stack. 15. The method of claim 14, wherein the conformal gate dielectric film is selected from a group consisting of: silicon dioxide, silicon oxynitride and hafnium oxide. 16. The method of claim 14, wherein the conformal metal gate film is selected from a group consisting of: tantalum nitride and titanium nitride. 17. The method of claim 1, wherein forming the second gate stack comprises: depositing a gate dielectric over the fins;depositing polysilicon over the gate dielectric; andpatterning the polysilicon and the gate dielectric to form the second gate stack. 18. The method of claim 1, further comprising forming a contact material on the epitaxial material. 19. The method of claim 18, wherein the contact material comprises a silicide, germanide or germanosilicide material. 20. The method of claim 1, further comprising thinning the nanowires after suspending the nanowires by: oxidizing the nanowires to form an oxide on the nanowires; andetching the oxide formed on the nanowires.
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이 특허에 인용된 특허 (2)
Doyle, Brian S.; Jin, Been-Yih; Kavalieros, Jack T.; Datta, Suman; Brask, Justin K.; Chau, Robert S., CMOS devices with a single work function gate electrode and method of fabrication.
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