초록 ▼

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extension

A planar transistor with improved performance has a source and a drain on a semiconductor substrate that includes a substantially undoped channel extending between the source and the drain. A gate is positioned over the substantially undoped channel on the substrate. Implanted source/drain extensions contact the source and the drain, with the implanted source/drain extensions having a dopant concentration of less than about 1×1019 atoms/cm3′, or alternatively, less than one-quarter the dopant concentration of the source and the drain.

대표청구항 ▼

1. A transistor without halo implants, comprising: a gate;a source region;a drain region;an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;a first highly doped layer below the channel layer and coextensive therewith;a second highly

1. A transistor without halo implants, comprising: a gate;a source region;a drain region;an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;a first highly doped layer below the channel layer and coextensive therewith;a second highly doped layer below the first highly doped layer and coextensive therewith;implanted source/drain extensions below the gate and extending toward each other from the source region and the drain region. 2. The transistor of claim 1, wherein the first highly doped layer establishes a threshold voltage for the transistor. 3. The transistor of claim 1, wherein the second highly doped layer sets a depletion depth for the transistor. 4. The transistor of claim 1, wherein the highly doped second layer has a greater dopant concentration that the highly doped first layer. 5. The transistor of claim 1, further comprising: a punch through suppression layer below the highly doped second layer. 6. The transistor of claim 5, wherein the punch through suppression layer has a dopant concentration less than the highly doped second layer. 7. The transistor of claim 1, further comprising: a single spacer in contact with the gate in order to separate the gate from the source region and the drain region. 8. The transistor of claim 1, wherein the channel layer is in contact with the highly doped first layer. 9. The transistor of claim 1, wherein the channel layer is in contact with the source region and the drain region. 10. The transistor of claim 1, wherein the undoped channel layer, the highly doped first layer, and the highly doped second layer are separate distinct layers. 11. The transistor of claim 1, wherein the dopant concentration of the implanted source/drain extensions is between one-quarter and one-twentieth of the dopant concentration of the respective source and drain. 12. The transistor of claim 1, wherein the implanted source/drain extensions have a dopant concentration of less than about 1×1019 atoms/cm3. 13. The transistor of claim 1, further comprising: a bias structure for modifying a threshold voltage of the transistor. 14. The transistor of claim 1, wherein the highly doped second layer has a dopant concentration between 5×1018 and 1×1020 atoms per cm3. 15. The transistor of claim 1, wherein the highly doped first layer has a dopant concentration between 1×1018 and 1×1019 atoms per cm3. 16. The transistor of claim 1, wherein the highly doped second layer is at a depth ranging from a length of the gate to one fifth of the length of the gate. 17. A die, comprising: a plurality of transistors, at least one of the plurality of transistors having: a gate;a source region;a drain region;an undoped epitaxially grown channel layer below the gate and extending between the source region and the drain region;a first highly doped layer below the channel layer and coextensive therewith;a second highly doped layer below the first highly doped layer and coextensive therewith;implanted source/drain extensions below the gate and extending toward each other from the source region and the drain region. 18. The transistor of claim 17, wherein the channel layer is in contact with the highly doped first layer. 19. The transistor of claim 17, wherein the channel layer is in contact with the source region and the drain region. 20. The transistor of claim 17, wherein the first highly doped layer establishes a threshold voltage for the transistor and the second highly doped layer sets a depletion depth for the transistor.