IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
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출원번호 |
US-0582715
(2009-10-21)
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등록번호 |
US-8564697
(2013-10-22)
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발명자
/ 주소 |
- Dong, Nguyen
- Mittra, Amit
- Lin, Chi-Shao
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 |
피인용 횟수 :
0 인용 특허 :
3 |
초록
▼
Black level calibration methods and systems are generally disclosed. According to one embodiment of the present invention, a method of calibrating a black level signal in a frame includes performing an iteration of averaging a first set of digital values corresponding to a first set of adjusted blac
Black level calibration methods and systems are generally disclosed. According to one embodiment of the present invention, a method of calibrating a black level signal in a frame includes performing an iteration of averaging a first set of digital values corresponding to a first set of adjusted black level signals associated with a first set of black pixels of the frame, determining whether an average value based on the first set of digital values has reached a target black level, determining a calibration offset based on a difference between the average value and the target black level and an accumulator step, converting the calibration offset to an analog signal, generating a calibration signal based on the analog signal for a second set of black pixels of the frame, and repeating the iteration for the frame until a predetermined condition is determined to have been met.
대표청구항
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1. A method for calibrating a black level signal in a frame, comprising: applying a first calibration signal to a first set of black level signals associated with a first set of black pixels of the frame to generate a first set of adjusted black level signals;averaging a first set of digital values
1. A method for calibrating a black level signal in a frame, comprising: applying a first calibration signal to a first set of black level signals associated with a first set of black pixels of the frame to generate a first set of adjusted black level signals;averaging a first set of digital values corresponding to the first set of adjusted black level signals;determining whether a first average value based on the first set of digital values has reached a target black level;if the first average value has not reached the target black level, then proceeding to determine a first calibration offset based on an accumulator step and a first difference between the first average value and the target black level;converting the first calibration offset to an analog signal;generating a second calibration signal based on the analog signal;applying the second calibration signal to a second set of black level signals associated with a second set of black pixels of the frame to generate a second set of adjusted black level signals;averaging a second set of digital values corresponding to the second set of adjusted black level signals; anddetermining whether a second average value based on the second set of digital values has reached the target black level and whether to proceed to determine a second calibration offset, wherein the second calibration offset is determined based on the accumulator step and a second difference between the second average value and the target black level. 2. The method of claim 1, wherein the determining a first calibration offset is further based on a black level ceiling. 3. The method of claim 1, further comprising: converting the second calibration offset to a second analog signal; andincluding the analog signal in the second analog signal. 4. The method of claim 1, wherein the converting the first calibration offset further comprises receiving the first calibration offset in a first bit resolution and outputting the analog signal in a second bit resolution. 5. The method of claim 1, further comprising determining whether to terminate calibration for the frame based on a predetermined condition, wherein the predetermined condition corresponds to having processed all black pixels in the frame. 6. A black level calibration (BLC) block configured to iteratively process a black level signal in a frame, the BLC block comprises: an averaging unit configured to calculate a first average value for a first set of digital values corresponding to a first set of adjusted black level signals associated with a first set of black pixels of the frame, wherein the first set of adjusted black level signals are generated based on a first calibration signal generated by a level integrator;a comparator configured to determine whether the first average value has reached a target black level and generate a first output signal based on a first difference between the first average value and the target black level;an accumulator configured to determine a first calibration offset based on the first output signal and an accumulator step, if the first average value has not reached the target black level;a digital-to-analog converter (DAC) configured to convert the first calibration offset to an analog signal;the level integrator configured to generate a second calibration signal based on the analog signal;the averaging unit configured to calculate a second average value for a second set of digital values corresponding to a second set of adjusted black level signals associated with a second set of black pixels of the frame, wherein the second set of adjusted black level signals are generated based on the second calibration signal; andthe comparator configured to determine whether the second average value has reached the target black level and whether to proceed to determine a second calibration offset, wherein the second calibration offset is determined based on the accumulator step and a second difference between the second average value and the target black level. 7. The BLC block of claim 6, wherein the comparator is further configured to compare the first difference between the first average value and the target black level to a black level ceiling in generating the first output signal for the accumulator. 8. The BLC block of claim 6, wherein the DAC is configured to convert the second calibration offset to a second analog signal, and the level integrator is configured to include the analog signal in the second analog signal. 9. The BLC block of claim 6, wherein the DAC is configured to receive the first calibration offset in a first bit resolution and output the analog signal in a second bit resolution. 10. The BLC block of claim 6, wherein the BLC block is configured to continue processing the black level signal in the frame until the BLC block has processed all black pixels in the frame. 11. An image processing system having a black level calibration (BLC) block configured to iteratively process a black level signal in a frame, the image processing system comprises: a summing junction configured to apply a first calibration signal from the BLC block to a first set of black level signals associated a first set of black pixels of the frame during a BLC period and generate a first set of adjusted black level signals;one or more analog-to-digital converters (ADCs) configured to convert the first set of adjusted black level signals to a first set of digital values; andthe BLC block havingan averaging unit configured to calculate a first average value for the first set of digital values;a comparator configured to determine whether the first average value has reached a target black level and generate a first output signal based on a first difference between the first average value and the target black level;an accumulator configured to determine a first calibration offset based on the first output signal and an accumulator step, if the first average value has not reached the target block level;a digital-to-analog converter (DAC) configured to convert the first calibration offset to an analog signal;a level integrator configured to generate a second calibration signal based on the analog signal for the summing junction to process a second set of black pixels of the frame;the averaging unit configured to calculate a second average value for a second set of digital values corresponding to a second set of adjusted black level signals associated with the second set of black pixels, wherein the second set of adjusted black level signals are generated based on the second calibration signal; andthe comparator configured to determine whether the second average value has reached the target black level and whether to proceed to determine a second calibration offset, wherein the second calibration offset is determined based on the accumulator step and a second difference between the second average value and the target black level. 12. The image processing system of claim 11, wherein after the BLC block has met a predetermined condition and exited the BLC period, the summing junction is configured to apply a calibration signal generated by the BLC block to active pixels of the frame. 13. The image processing system of claim 11, wherein the comparator of the BLC block is further configured to compare the first difference between the first average value and the target black level to a black level ceiling in generating the first output signal for the accumulator. 14. The image processing system of claim 11, wherein the DAC is configured to convert the second calibration offset to a second analog signal, and the level integrator of the BLC block is configured to include the analog signal in the second analog signal. 15. The image processing system of claim 11, wherein the one or more ADCs are configured to generate the first set of digital values at a first bit resolution, and the DAC of the BLC block is configured to output the analog signal in a second bit resolution. 16. The image processing system of claim 12, wherein the predetermined condition corresponds to an average value for a set of black pixels in the frame having reached the target black level. 17. The image processing system of claim 11, wherein the predetermined condition corresponds to the BLC block having processed all black pixels in the frame. 18. The image processing system of claim 11, wherein the one or more ADCs are configured to independently handle distinct color channels of the frame.
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