초록 ▼

A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least th

A two-step hydrogen anneal process has been developed for use in fabricating semiconductor nanowires for use in non-planar semiconductor devices. In the first part of the two-step hydrogen anneal process, which occurs prior to suspending a semiconductor nanowire, the initial roughness of at least the sidewalls of the semiconductor nanowire is reduced, while having at least the bottommost surface of the nanowire pinned to an uppermost surface of a substrate. After performing the first hydrogen anneal, the semiconductor nanowire is suspended and then a second hydrogen anneal is performed which further reduces the roughness of all exposed surfaces of the semiconductor nanowire and reshapes the semiconductor nanowire. By breaking the anneal into two steps, smaller semiconductor nanowires at a tight pitch survive the process and yield.

대표청구항 ▼

1. A method of fabricating a semiconductor nanowire comprising: forming at least one semiconductor nanowire from at least an uppermost semiconductor layer of a substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor pad region and another en

1. A method of fabricating a semiconductor nanowire comprising: forming at least one semiconductor nanowire from at least an uppermost semiconductor layer of a substrate, wherein an end segment of said at least one semiconductor nanowire is attached to a first semiconductor pad region and another end segment of said at least one semiconductor nanowire is attached to a second semiconductor pad region;performing a first hydrogen anneal on said at least one semiconductor nanowire with at least a bottommost surface of said at least one semiconductor nanowire in direct contact with an uppermost surface of said substrate;removing a portion of said substrate located beneath said at least one semiconductor nanowire to suspend said at least one semiconductor nanowire above a remaining portion of said substrate; andperforming a second hydrogen anneal on said at least one semiconductor nanowire that is suspended above the remaining portion of said insulator layer. 2. The method of claim 1, wherein during said first hydrogen anneal, an uppermost surface of the at least one semiconductor material is protected by a patterned mask. 3. The method of claim 1, wherein said first hydrogen anneal is performed at a temperature from 600° C. to 1000° C. at a hydrogen pressure of from 7 torr to 600 torr. 4. The method of claim 1, wherein said removing the portion of said substrate located beneath said at least one semiconductor nanowire comprises an isotropic etching process. 5. The method of claim 1, wherein said second hydrogen anneal is performed at a temperature from 600° C. to 1000° C. at a hydrogen pressure of from 7 torr to 600 torr. 6. The method of claim 1, wherein said first hydrogen anneal is performed at a temperature, pressure or temperature and pressure which is greater than a temperature, pressure or temperature and pressure of said second hydrogen anneal. 7. The method of claim 1, further comprising performing an oxidation process at a temperature of greater than 700° C. and etching grown oxide to thin said at least one semiconductor nanowire after performing said second hydrogen anneal. 8. The method of claim 1, further comprising growing a chemical oxide from the at least one semiconductor nanowire and etching grown oxide to thin said at least one semiconductor nanowire after performing said second hydrogen anneal. 9. The method of claim 1, wherein said at least one semiconductor nanowire prior to performing said first hydrogen anneal has a first roughness, said at least one semiconductor nanowire after said performing the first hydrogen anneal and prior to performing the second hydrogen anneal has a second roughness, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third roughness, wherein said first roughness is greater than the second roughness, and said second roughness is greater than the third roughness. 10. The method of claim 9, wherein said first roughness, expressed in terms of a mean squared roughness, is from 0.5 nm to 5 nm, said second roughness, expressed in terms of a mean squared roughness, is from 0.3 nm to 2 nm, and said third roughness, expressed in terms of a mean squared roughness, is from 0.1 nm to 1 nm. 11. The method of claim 1, wherein said at least one semiconductor nanowire prior to performing said first hydrogen anneal has a first width, said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said first width, said second width and said third width are substantially the same. 12. The method of claim 1, wherein said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said second width is greater than said third width. 13. The method of claim 1, wherein said at least one semiconductor nanowire after performing said first hydrogen anneal and prior to performing said second hydrogen anneal has a second width, and said at least one semiconductor nanowire after performing said second hydrogen anneal has a third width, wherein said second width is less than said third width. 14. The method of claim 1, wherein said at least one semiconductor nanowire comprises a plurality of semiconductor nanowires, wherein a pitch between each of the semiconductor nanowires is from 5 nm to 70 nm. 15. The method of claim 1, wherein substrate further includes at least one other semiconductor layer beneath the uppermost semiconductor layer, said at least one other semiconductor layer comprises a different semiconductor material than the uppermost semiconductor layer. 16. The method of claim 1, wherein said substrate further includes an insulator layer located directly beneath the uppermost semiconductor layer.