초록 ▼

Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whe

Disclosed is a memory array structure, where a wordline driver selectively applies a high on-state voltage (VWLH) or a low off-state voltage (VWLL) to a wordline. VWLH has a slightly negative temperature coefficient so that it is regulated as high as the gate dielectric reliability limits allow, whereas VWLL has a substantially neutral temperature coefficient. To accomplish this, the wordline driver is coupled to one or more voltage regulation circuits. In one embodiment, the wordline driver is coupled to a single voltage regulation circuit, which incorporates a single voltage reference circuit having a single output stage that outputs multiple reference voltages. Also disclosed is a voltage reference circuit, which can be incorporated into the voltage regulation circuit of a memory array structure, as described, or, alternatively, into any other integrated circuit structure requiring voltages with different temperature coefficients. Also disclosed is a method of operating a memory array structure.

대표청구항 ▼

1. A memory array structure comprising: a plurality of memory cells;a wordline operatively connected to said memory cells;a wordline driver coupled to a first node at a relatively high on-state voltage, to a second node at a relatively low off-state voltage and to said wordline, said wordline driver

1. A memory array structure comprising: a plurality of memory cells;a wordline operatively connected to said memory cells;a wordline driver coupled to a first node at a relatively high on-state voltage, to a second node at a relatively low off-state voltage and to said wordline, said wordline driver selectively applying one of said relatively high on-state voltage and said relatively low off-state voltage to said wordline, said relatively high on-state voltage having a negative temperature coefficient and said relatively low off-state voltage having a substantially neutral temperature coefficient; and,a voltage regulation circuit providing said on-state voltage to said first node and, thereby to said wordline driver and further providing said off-state voltage to said second node and, thereby to said wordline driver. 2. The memory array structure of claim 1, said negative temperature coefficient ensuring that an increase in an operating temperature of said memory array structure causes a decrease in said on-state voltage in order to minimize any reliability degradation caused by a corresponding decrease in gate dielectric reliability with said increase in said operating temperature. 3. The memory array structure of claim 1, said negative temperature coefficient ensuring that said on-state voltage ranges from approximately 1.670V at −25° C. to approximately 1.600V at 125° C. 4. The memory array structure of claim 1, said voltage regulation circuit comprising: a voltage reference circuit having an output stage outputting a first reference voltage with said negative temperature coefficient and a second reference voltage with said substantially neutral temperature coefficient;a first voltage regulator receiving said first reference voltage from said output stage;a positive voltage pump being electrically connected in a first feedback loop with said first voltage regulator and outputting said on-state voltage with said negative temperature coefficient to said first node and, thereby to said wordline driver;a second voltage regulator receiving said second reference voltage from said output stage; anda negative voltage pump being electrically connected in a second feedback loop with said second voltage regulator and outputting said off-state voltage with said substantially neutral temperature coefficient to said second node and, thereby to said wordline driver. 5. The memory array structure of claim 4, said voltage reference circuit comprising a bandgap voltage reference circuit. 6. A memory array structure comprising: a voltage regulation circuit comprising:a voltage reference circuit outputting a first reference voltage with a negative temperature coefficient and a second reference voltage with a substantially neutral temperature coefficient;a first voltage regulator receiving said first reference voltage;a positive voltage pump being electrically connected in a first feedback loop with said first voltage regulator and outputting an on-state voltage with said negative temperature coefficient;a second voltage regulator receiving said second reference voltage; anda negative voltage pump being electrically connected in a second feedback loop with said second voltage regulator and outputting an off-state voltage with said substantially neutral temperature coefficient;a plurality of memory cells;a wordline operatively connected to said memory cells; anda wordline driver coupled between said voltage regulation circuit and said wordline, said wordline driver selectively applying one of said on-state voltage and said off-state voltage to said wordline. 7. The memory array structure of claim 6, said negative temperature coefficient ensuring that an increase in an operating temperature of said memory array structure causes a decrease in said on-state voltage in order to minimize any reliability degradation caused by a corresponding decrease in gate dielectric reliability with said increase in said operating temperature. 8. The memory array structure of claim 6, said negative temperature coefficient ensuring that said on-state voltage ranges from approximately 1.670V at −25° C. to approximately 1.600V at 125° C. 9. The memory array structure of claim 6, said voltage reference circuit comprising an output stage comprising: a pair of current sources comprising: a first current source outputting a first current having a negative temperature coefficient;a second current source outputting a second current having a positive temperature coefficient;a resistive network electrically connecting said first current source, said second current source and ground at a single node, said resistive network comprising: a first resistor, a second resistor and a third resistor connected in series between ground and said second current source; anda fourth resistor connected in series between said node and said first current source, said node being positioned between said first resistor and said second resistor; anda plurality of taps electrically connected to said resistive network at different locations, said first current and said second current mixing in said resistive network such that voltages at said taps have different temperature coefficients. 10. The memory array structure of claim 9, said plurality of taps comprising: a first tap electrically connected to said resistive network between said first resistor and said second resistor such that said first reference voltage on said first tap has said negative temperature coefficient; anda second tap electrically connected to said resistive network between said second resistor and said second current source such that said second reference voltage on said second tap has said substantially neutral temperature coefficient. 11. The memory array structure of claim 6, said voltage reference circuit comprising a bandgap reference circuit. 12. A voltage reference circuit comprising: a pair of current sources comprising: a first current source outputting a first current having a negative temperature coefficient;a second current source outputting a second current having a positive temperature coefficient;a resistive network electrically connecting said first current source, said second current source and ground at a single node; anda plurality of taps electrically connected to said resistive network at different locations, said first current and said second current mixing in said resistive network such that reference voltages at said taps have different temperature coefficients, said resistive network comprising:a first resistor, a second resistor and a third resistor connected in series between ground and said second current source; anda fourth resistor connected in series between said node and said first current source, said node being positioned between said first resistor and said second resistor. 13. The voltage reference circuit of claim 12, further comprising a bandgap voltage reference circuit having a single output stage comprising said pair of current sources, said resistive network and said plurality of taps. 14. The voltage reference circuit of claim 12, said plurality of taps comprising a first tap electrically connected to said resistive network between said first resistor and said second resistor such that a first reference voltage on said first tap has a relatively small negative temperature coefficient. 15. The voltage reference circuit of claim 12, said plurality of taps comprising a second tap electrically connected to said resistive network between said second resistor and said third resistor such that a second reference voltage on said second tap has a neutral temperature coefficient. 16. The voltage reference circuit of claim 12, said plurality of taps comprising a third tap electrically connected to said resistive network adjacent to said third resistor such that a third reference voltage on said third tap has a positive temperature coefficient. 17. The voltage reference circuit of claim 12, said plurality of taps comprising a fourth tap on said resistive network adjacent to said fourth resistor such that a fourth voltage on said fourth tap has a relatively large negative temperature coefficient. 18. A method of operating a memory array structure comprising a wordline operatively connected to a plurality of memory cells, said method comprising: supplying, by a voltage regulation circuit, a relatively high on-state voltage to a first node and a relatively low off-state voltage to a second node, said first node and said second node each being electrically coupled to a wordline driver and said wordline driver further being electrically coupled to said wordline; and,selectively applying, by said wordline driver to said wordline, one of said relatively high on-state voltage and said relatively low off-state voltage,said relatively high on-state voltage having a negative temperature coefficient and said relatively low off-state voltage having a substantially neutral temperature coefficient. 19. The method of claim 18, said negative temperature coefficient ensuring that an increase in an operating temperature of said memory array structure causes a decrease in said on-state voltage in order to minimize any reliability degradation caused by a corresponding decrease in gate dielectric reliability with said increase in said operating temperature. 20. The method of claim 18, said negative temperature coefficient ensuring that said on-state voltage ranges from approximately 1.670V at −25° C. to approximately 1.600V at 125° C.