Si and SiGeC on a buried oxide layer on a substrate
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/84
H01L-021/762
H01L-027/12
H01L-021/8238
H01L-021/8249
H01L-027/06
H01L-027/092
출원번호
US-0150440
(2011-06-01)
등록번호
US-9087925
(2015-07-21)
발명자
/ 주소
Liu, Xuefeng
Rassel, Robert M.
Voldman, Steven H.
출원인 / 주소
INTERNATIONAL BUSINESS MACHINES CORPORATION
대리인 / 주소
Canale, Anthony
인용정보
피인용 횟수 :
1인용 특허 :
13
초록▼
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. Th
Semiconductor structures and methods of forming semiconductor structures, and more particularly to structures and methods of forming SiGe and/or SiGeC buried layers for SOI/SiGe devices. An integrated structure includes discontinuous, buried layers having alternating Si and SiGe or SiGeC regions. The structure further includes isolation structures at an interface between the Si and SiGe or SiGeC regions to reduce defects between the alternating regions. Devices are associated with the Si and SiGe or SiGeC regions.
대표청구항▼
1. An integrated structure, comprising: a buried oxide (BOX) layer on a substrate;discontinuous, buried layers having alternating Si and SiGe or SiGeC regions, directly contacting a Si layer formed on the BOX layer;isolation structures at an interface of the Si and SiGe or SiGeC regions to reduce de
1. An integrated structure, comprising: a buried oxide (BOX) layer on a substrate;discontinuous, buried layers having alternating Si and SiGe or SiGeC regions, directly contacting a Si layer formed on the BOX layer;isolation structures at an interface of the Si and SiGe or SiGeC regions to reduce defects between the alternating regions; anddevices associated with the Si and SiGe or SiGeC regions,wherein bottom surfaces of the Si and SiGe or SiGeC regions and the isolation structures are formed within a same plane on an upper surface of the Si layer. 2. The integrated structure of claim 1, wherein the BOX layer is under the SiGe and SiGeC regions and the Si layer. 3. The integrated structure of claim 2, wherein the SiGe or SiGeC regions are in troughs formed in the Si layer. 4. The integrated structure of claim 2, wherein the isolation structures are above the BOX layer and extend above top surfaces of the SiGe or SiGeC regions. 5. The integrated structure of claim 2, wherein the troughs are above the BOX layer and the Si regions are in troughs formed in a SiGe or SiGeC layer. 6. The integrated structure of claim 1, wherein SiGe or SiGeC layers are non-doped, or n-typed doped or p-typed doped. 7. The integrated structure of claim 1, wherein the isolation structures comprise at least one of a shallow trench isolation structure, a deep trench isolation structure and a trench isolation structure, directly contacting the Si layer. 8. The structure of claim 1, wherein the isolation structures at the interface between the Si and SiGe or SiGeC regions are directly contacting the underlying Si layer. 9. The structure of claim 1, wherein the Si and SiGe or SiGeC regions are of different thicknesses, formed on a same level. 10. The structure of claim 9, wherein an Si epi layer is above and in direct contact with the SiGe or SiGeC regions. 11. An integrated structure, comprising: a substrate;alternating Si and SiGe or SiGeC regions formed directly on the substrate, wherein bottom surfaces of the Si and SiGe or SiGeC regions are formed within a same plane on the substrate and portions of the Si regions extend above top surfaces of the SiGe or SiGeC regions;isolation structures at an interface between the alternating Si and SiGe or SiGeC regions and in contact with the substrate;a buried oxide (BOX) layer formed above the substrate and the alternating SiGe or SiGeC regions;a first type device associated with the Si regions; anda second type device associated with the SiGe or SiGeC regions. 12. The integrated structure of claim 11, wherein the SiGe or SiGeC regions are in troughs formed in an Si layer. 13. The integrated structure of claim 11, wherein the SiGe or SiGeC regions are non-doped, or n-typed doped or p-typed doped. 14. The structure of claim 11, wherein the BOX layer is between the alternating SiGe or SiGeC regions and an overlying Si layer. 15. The structure of claim 14, wherein the BOX layer is directly in contact with the alternating SiGe or SiGeC regions and the overlying Si layer. 16. A structure, comprising: a substrate;a buried oxide layer over the substrate;a Si film over the substrate and a buried oxide layer;a Si material over the Si film;SiGe or SiGeC material in troughs of the Si material to form alternating Si regions with SiGe or SiGeC regions, wherein the Si film is directly under the Si material and the SiGe or SiGeC material;isolation structures at interfaces between the SiGe or SiGeC regions and the alternating Si regions, wherein upper surfaces of the isolation structures are coplanar to top surfaces of the SiGe or SiGeC regions; andan epitaxial layer over and contacting each of: the SiGe or SiGeC regions and the Si regions,wherein bottom surfaces of the Si material, the SiGe or SiGeC regions, and the isolation structures are formed within a same plane on a surface of the Si film. 17. The structure of claim 16, wherein the buried oxide layer is formed under the SiGe or SiGeC regions. 18. The structure of claim 17, wherein the SiGe or SiGeC regions are non-doped, or n-typed doped or p-typed doped. 19. The structure of claim 18, further comprising a first type device over the Si regions and a second type device over the SiGe or SiGeC regions.
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이 특허에 인용된 특허 (13)
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Thean,Voon Yew; Goolsby,Brian J.; McCormick,Linda B.; Nguyen,Bich Yen; Parker,Colita M.; Sadaka,Mariam G.; Vartanian,Victor H.; White,Ted R.; Zavala,Melissa O., Electronic devices including a semiconductor layer and a process for forming the same.
Christiansen, Silke H.; Grill, Alfred; Mooney, Patricia M., Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same.
Meunier Beillard, Philippe; Ravit, Claire, Method of manufacturing a strained semiconductor layer, method of manufacturing a semiconductor device and semiconductor substrate suitable for use in such a method including having a thin delta profile layer of germanium close to the bottom of the strained layer.
Yu, Bin; En, William G.; An, Judy Xilin; Riccobene, Concetta E., Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding.
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