초록 ▼

A readout transistor circuit for a pixel is disclosed. The readout transistor circuit includes a sense node. A reset transistor is in signal communication with the sense node. A source follower transistor is in signal communication with the sense node. A row select transistor is in signal communicat

A readout transistor circuit for a pixel is disclosed. The readout transistor circuit includes a sense node. A reset transistor is in signal communication with the sense node. A source follower transistor is in signal communication with the sense node. A row select transistor is in signal communication with the source follower transistor. A switching transistor is in signal communication with the sense node. A capacitor is in signal communication with the switching transistor. The switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e−) ratio and a high voltage-per-charge (V/e−) to enable low noise performance of the sense node. The capacitor may be a metal-insulator-metal (MIM) capacitor. At least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor may be a MOSFET. One or more of the MOSFETs may be a buried channel MOSFET.

대표청구항 ▼

1. A readout transistor circuit for a pixel, comprising: a sense node of a back-illuminated CMOS imager pixel;a reset transistor in signal communication with the sense node;a source follower transistor in signal communication with the sense node;a row select transistor in signal communication with t

1. A readout transistor circuit for a pixel, comprising: a sense node of a back-illuminated CMOS imager pixel;a reset transistor in signal communication with the sense node;a source follower transistor in signal communication with the sense node;a row select transistor in signal communication with the sense node;a switching transistor in signal communication with the sense node, the switching transistor connected to a source terminal of the reset transistor; anda capacitor connected between a source terminal of the switching transistor and ground,wherein the switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e−) ratio and a high voltage-per-charge (V/e−) to enable low noise performance of the sense node. 2. The readout transistor circuit of claim 1, wherein the capacitor is a metal insulator-metal (MIM) capacitor. 3. The readout transistor circuit of claim 2, wherein the metal-insulator-metal (MIM) capacitor is connected in a series with the switching transistor and the reset transistor, the MIM capacitor coupled between the switching transistor and the reset transistor. 4. The readout transistor of claim 3, wherein the switching transistor is connected in parallel with the reset transistor. 5. The readout transistor circuit of claim 1, wherein at least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor is a MOSFET. 6. The readout transistor circuit of claim 5, wherein at least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor is a buried channel MOSFET. 7. The readout transistor circuit of claim 1, wherein the sense node comprises a photon-to-charge-converter comprising at least one of a pinned photo diode (PPD), a photo-gate, and a photodiode. 8. The readout transistor circuit of claim 1, further comprising: a source follower transistor in signal communication with the row select transistor for outputting an analog electrical signal derived from the sense node to a column line, andat least one of an analog signal processor and an analog-to-digital converter (ADC) in signal communication with the column line. 9. An imager, comprising: a pixel array of CMOS imaging pixels comprising a plurality of pixels arranged in a predetermined number of columns and rows selected by a plurality of column select lines and row select lines, respectively;wherein each pixel of the pixel array comprises: a sense node;a reset transistor in signal communication with the sense node;a source follower transistor in signal communication with the sense node;a row select transistor in signal communication with the source follower transistor;a switching transistor in signal communication with the sense node, the switching transistor connected to a source terminal of the reset transistor; anda capacitor between a source terminal of the switching transistor and ground;wherein the switching transistor is configured to place the capacitor in signal communication with the sense node to switch between a low voltage-per-charge (V/e−) ratio and a high voltage-per-charge (V/e−) to enable low noise performance of the sense node. 10. The imager of claim 9, wherein the capacitor is a metal-insulator-metal (MIM) capacitor. 11. The readout transistor circuit of claim 10, wherein the metal-insultator-metal (MIM) capacitor is connected in a series with the switching transistor and the reset transistor, the MIM capacitor coupled between the switching transistor and the reset transistor. 12. The imager of claim 11, wherein at least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor is a MOSFET. 13. The imager of claim 12, wherein at least one of the reset transistor, the source follower transistor, the row select transistor, and the switching transistor is a buried channel MOSFET. 14. The imager of claim 11, wherein the sense node comprises a photon-to-charge converter comprising a least one of a pinned photo diode (PPD), a photo-gate, and a photodiode. 15. The imager of claim 11, further comprising: a source follower transistor in signal communication with the row select transistor for outputting an analog electrical signal derived from the sense node to a column line, andat least one of an analog signal processor and an analog-to-digital converter (ADC) in signal communication with the column line. 16. The imager of claim 15, further comprising: a row driver and a row address decoder in signal communication with the row driver, wherein the row driver is configured for selectively activating at least one of row select lines in response to a row address decoder;a column driver and a column address decoder in signal communication with the column driver for selectively activating at least one of column select lines in response to the column address decoder;a control circuit for controlling the row address decoder and column address decoder for selecting at least one row and column line for pixel readout; androw and column driver circuitry configured for driving voltage to drive transistors of the selected at least one row and column lines. 17. The imager of claim 16, further comprising a processor in signal communication with at least one of an analog signal processor and an analog-to-digital converter (ADC). 18. The imager of claim 17, wherein the processor employs a digital correlated double sampling method whereby a reference sample and a signal sample are differenced on a pixel-by-pixel basis. 19. The imager of claim 9, wherein the switching transistor is connected in parallel with the reset transistor. 20. The method for reading a pixel in a CMOS imager array, wherein the pixel comprises a sense node; a reset transistor in a signal communication with the sense node; a source follower transistor in signal communication with the sense node; a row select transistor in signal communication with the source follower transistor; a switching transistor in signal communication with the sense node; a capacitor connected between a source terminal of the switching transistor and ground; and further comprising an analog correlated double sampling circuit having a clamp switch and an analog to digital converter (ADC), the method comprising: operating the reset transistor and switching transistor (on and off) to reset the sense node;operating the clamp switch (on and off);activating a transfer gate of the pixel (on and off) to transfer charge to a sense node;sample and holding a column voltage selected by the row select transistor; andreading an output of the ADC to obtain a high uV/e− sample;turning the switching transistor on to switch between high uV/e− ratio and low uV/e− positions;repeating the activating, sample and holding, and reading processes to obtain a low uV/e− sample. 21. The method of claim 20, further comprising storing the high uV/e− sample and the low uV/e− sample in the processor. 22. The method of claim 20, wherein the reset transistor, switching transistor, clamp switch, and transfer gate are operated on and off.