Method for manufacturing LTPS TFT substrate and LTPS TFT substrate
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IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-027/12
H01L-021/02
H01L-029/66
H01L-021/265
출원번호
US-0771502
(2015-06-29)
등록번호
US-9520421
(2016-12-13)
국제출원번호
PCT/CN2015/082667
(2015-06-29)
발명자
/ 주소
Li, Songshan
출원인 / 주소
SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
대리인 / 주소
Lei, Leong C.
인용정보
피인용 횟수 :
2인용 특허 :
0
초록▼
The present invention provides a method for manufacturing a LTPS TFT substrate and a LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate of the present invention forms a thermally conductive electrical insulation layer having excellent properties of electrical insulation and ther
The present invention provides a method for manufacturing a LTPS TFT substrate and a LTPS TFT substrate. The method for manufacturing the LTPS TFT substrate of the present invention forms a thermally conductive electrical insulation layer having excellent properties of electrical insulation and thermal conductivity on a buffer layer to quickly absorb a great amount of heat during a RTA process to be transferred to an amorphous silicon layer in contact therewith so that the portion of the amorphous silicon at this site shows an increased efficiency of crystallization, whereby polycrystalline silicon has an increased grain size and reduced gain boundaries and thus the mobility of charge carriers of a corresponding TFT device is increased and the influence of the leakage current caused by grain boundary is reduced. The LTPS TFT substrate of the present invention includes a thermally conductive electrical insulation layer formed on a buffer layer at a location exactly under a polycrystalline silicon semiconductor layer and the grain size of the crystallization of the polycrystalline silicon is relatively large, the grain boundaries are reduced in number, the mobility of charge carriers of a TFT device is increased, and the electrical property of the TFT is improved.
대표청구항▼
1. A method for manufacturing a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a substrate and depositing a buffer layer on the substrate;(2) depositing a thermally conductive electrical insulation film on the buffer
1. A method for manufacturing a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a substrate and depositing a buffer layer on the substrate;(2) depositing a thermally conductive electrical insulation film on the buffer layer and patterning the thermally conductive electrical insulation film to form a thermally conductive electrical insulation layer;(3) depositing an amorphous silicon layer on the buffer layer in such a way that the amorphous silicon layer completely covers the thermally conductive electrical insulation layer;(4) implanting boron ions in the amorphous silicon layer through ion implantation; subjecting the amorphous silicon layer to rapid thermal annealing to have the amorphous silicon crystallized into polycrystalline silicon, and then applying an etching operation to remove an electrically conductive layer precipitating on a surface of the polycrystalline silicon during crystallization to form a polycrystalline silicon layer;(5) patterning the polycrystalline silicon layer to form a polycrystalline silicon semiconductor layer;(6) coating photoresist on the polycrystalline silicon semiconductor layer and conducting exposure and development on the photoresist to form a photoresist layer on the polycrystalline silicon semiconductor layer in such a way that two end portions of the polycrystalline silicon semiconductor layer are exposed; implanting boron ions into the two end portions of the polycrystalline silicon semiconductor layer through ion implantation with the photoresist layer serving as a shielding layer so as to form source/drain contact zones; and(7) peeling off the photoresist layer and forming, in sequence, a gate insulation layer, a gate terminal, an interlayer insulation layer, and source/drain terminals on the polycrystalline silicon semiconductor layer, wherein the source/drain terminals are respectively connected to the source/drain contact zones at the two end portions of the polycrystalline silicon semiconductor layer. 2. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (1), the buffer layer is formed of a material of SiNx, SiOx, or a combination thereof. 3. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (2), photolithographic and etching operations are applied to pattern the thermally conductive electrical insulation layer; the thermally conductive electrical insulation layer is formed of a material of Al2O3; and the thermally conductive electrical insulation layer has a thickness of 30-50 nm. 4. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (3), the amorphous silicon layer has a thickness of 200-300 nm. 5. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (4), the rapid thermal annealing is conducted at a temperature of 650° C.-700° C. for a time period of 15-25 minutes; and the electrically conductive layer that precipitates on the surface of the polycrystalline silicon is removed through etching by a thickness of 100-150 nm. 6. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (5), photolithographic and etching operations are applied to pattern the polycrystalline silicon layer; and the pattern of the thermally conductive electrical insulation layer corresponds to the pattern of the polycrystalline silicon semiconductor layer. 7. The method for manufacturing the LTPS TFT substrate as claimed in claim 1, wherein in step (7), the gate insulation layer is formed of a material of SiOx. 8. A method for manufacturing a low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) substrate, comprising the following steps: (1) providing a substrate and depositing a buffer layer on the substrate;(2) depositing a thermally conductive electrical insulation film on the buffer layer and patterning the thermally conductive electrical insulation film to form a thermally conductive electrical insulation layer;(3) depositing an amorphous silicon layer on the buffer layer in such a way that the amorphous silicon layer completely covers the thermally conductive electrical insulation layer;(4) implanting boron ions in the amorphous silicon layer through ion implantation; subjecting the amorphous silicon layer to rapid thermal annealing to have the amorphous silicon crystallized into polycrystalline silicon, and then applying an etching operation to remove an electrically conductive layer precipitating on a surface of the polycrystalline silicon during crystallization to form a polycrystalline silicon layer;(5) patterning the polycrystalline silicon layer to form a polycrystalline silicon semiconductor layer;(6) coating photoresist on the polycrystalline silicon semiconductor layer and conducting exposure and development on the photoresist to form a photoresist layer on the polycrystalline silicon semiconductor layer in such a way that two end portions of the polycrystalline silicon semiconductor layer are exposed; implanting boron ions into the two end portions of the polycrystalline silicon semiconductor layer through ion implantation with the photoresist layer serving as a shielding layer so as to form source/drain contact zones; and(7) peeling off the photoresist layer and forming, in sequence, a gate insulation layer, a gate terminal, an interlayer insulation layer, and source/drain terminals on the polycrystalline silicon semiconductor layer, wherein the source/drain terminals are respectively connected to the source/drain contact zones at the two end portions of the polycrystalline silicon semiconductor layer;wherein in step (1), the buffer layer is formed of a material of SiNx, SiOx, or a combination thereof;wherein in step (2), photolithographic and etching operations are applied to pattern the thermally conductive electrical insulation layer; the thermally conductive electrical insulation layer is formed of a material of Al2O3; and the thermally conductive electrical insulation layer has a thickness of 30-50 nm;wherein in step (3), the amorphous silicon layer has a thickness of 200-300 nm. 9. The method for manufacturing the LTPS TFT substrate as claimed in claim 8, wherein in step (4), the rapid thermal annealing is conducted at a temperature of 650° C.-700° C. for a time period of 15-25 minutes; and the electrically conductive layer that precipitates on the surface of the polycrystalline silicon is removed through etching by a thickness of 100-150 nm. 10. The method for manufacturing the LTPS TFT substrate as claimed in claim 8, wherein in step (5), photolithographic and etching operations are applied to pattern the polycrystalline silicon layer; and the pattern of the thermally conductive electrical insulation layer corresponds to the pattern of the polycrystalline silicon semiconductor layer. 11. The method for manufacturing the LTPS TFT substrate as claimed in claim 8, wherein in step (7), the gate insulation layer is formed of a material of SiOx. 12. A low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) substrate, comprising a substrate, a buffer layer arranged on the substrate, a thermally conductive electrical insulation layer arranged on the buffer layer, a polycrystalline silicon semiconductor layer arranged on the thermally conductive electrical insulation layer, a gate insulation layer arranged on the buffer layer and covering the thermally conductive electrical insulation layer and the polycrystalline silicon semiconductor layer, a gate terminal arranged on the gate insulation layer, an interlayer insulation layer arranged on the gate insulation layer and covering the gate terminal, and source/drain terminals arranged on the interlayer insulation layer; wherein the polycrystalline silicon semiconductor layer has two opposite end portions that are source/drain contact zones implanted with boron ions; the gate insulation layer and the interlayer insulation layer both have portions corresponding to the source/drain contact zones and formed with vias; and the source/drain terminals are respectively connected through the vias to the source/drain contact zones. 13. The LTPS TFT substrate as claimed in claim 12, wherein the buffer layer is formed of a material of SiNx, SiOx, or a combination thereof; the thermally conductive electrical insulation layer is formed of a material of Al2O3; and the gate insulation layer is formed of a material of SiOx. 14. The LTPS TFT substrate as claimed in claim 12, wherein the thermally conductive electrical insulation layer has a thickness of 30-50 nm; the thermally conductive electrical insulation layer has a pattern corresponding to a pattern of the polycrystalline silicon semiconductor layer.
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