SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
대리인 / 주소
Lei, Leong C.
인용정보
피인용 횟수 :
1인용 특허 :
2
초록▼
The invention provides a manufacturing method for LTPS TFT substrate. After forming N+ areas on both sides of polysilicon layer, the first gate insulating layer, first gate, second gate insulating layer, and second gate are sequentially formed on polysilicon layer, and the second gate is wider than
The invention provides a manufacturing method for LTPS TFT substrate. After forming N+ areas on both sides of polysilicon layer, the first gate insulating layer, first gate, second gate insulating layer, and second gate are sequentially formed on polysilicon layer, and the second gate is wider than first gate to produce a low electric field region in the polysilicon layer to reduce leakage current; alternatively, forming first gate and first gate insulating layer, forming polysilicon layer and N+ areas on both sides of polysilicon layer, forming second gate insulating layer and second gate on polysilicon layer, the second gate insulating layer is thicker than first gate insulating layer and the second gate is wider than first gate, so that the second gate insulating layer sandwiched by the second gate beyond first gate and polysilicon layer is thicker and produces a smaller electric field, which simplifies process and reduce cost.
대표청구항▼
1. A manufacturing method for low temperature polysilicon (LTPS) thin film transistor (TFT) substrate, which comprises: Step 1: providing a substrate, and depositing a buffer layer on the substrate;Step 2: depositing an amorphous silicon (a-Si) layer on the buffer layer, performing dehydrogenation t
1. A manufacturing method for low temperature polysilicon (LTPS) thin film transistor (TFT) substrate, which comprises: Step 1: providing a substrate, and depositing a buffer layer on the substrate;Step 2: depositing an amorphous silicon (a-Si) layer on the buffer layer, performing dehydrogenation treatment on the a-Si layer, performing a crystallization process to turn the a-Si layer into a polysilicon layer, and patterning the polysilicon layer to obtain an island-shape polysilicon layer;Step 3: coating a photo-resist on the island-shape polysilicon layer and performing exposure and development on the photo-resist to form a photo-resist layer; using the photo-resist layer as a masking layer to perform ion implantation on both sides of the island-shape polysilicon layer to form an N-type heavily doped (N+) area on the both sides of the island-shape polysilicon layer and an undoped area between the two N+ areas, and then peeling the photo-resist layer off;Step 4: depositing a first gate insulating layer on the island-shape polysilicon gate layer, depositing a first metal layer on the first gate insulating layer, and patterning the first metal layer to obtain a corresponding first gate above the undoped area, and the first gate having a width smaller than a width of the undoped area;Step 5: depositing a second gate insulating layer on the first gate insulating layer and the first gate, depositing a second metal layer on the second gate insulating layer, patterning the second metal layer to obtain a corresponding second gate above the first gate, the second gate having a width equal to the width of the undoped area, and the both ends of the second gate extending beyond the both ends of the first gate so that a portion of the undoped area covered by the first gate and the second gate forms a groove area with a strong electric field, and the portion of the undoped area covered only by the second gate forming a low electric field area;Step 6: depositing an interlayer insulating layer between the second gate insulting layer and the second gate; performing a lithography process to form vias on the interlayer insulating layer, the first gate insulating layer, and the second gate insulating layer over the N+ areas on the both sides of the island-shape polysilicon layer; andStep 7: depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain a source and a drain, the source and the drain contacting through the vias the N+ areas on the both sides of the island-shape polysilicon layer. 2. The manufacturing method for LTPS TFT substrate as claimed in claim 1, wherein in Step 1, the substrate is a glass substrate; the buffer layer is a laminant layer with a silicon nitride layer and a silicon oxide layer; the thickness of the silicon nitride layer is 40-100 nm; the thickness of the silicon oxide layer is 100-200 nm. 3. The manufacturing method for LTPS TFT substrate as claimed in claim 1, wherein in Step 3, the thickness of the a-Si layer is 40-60 nm; the crystallization process is an excimer laser annealing or solid-phase crystallization process. 4. The manufacturing method for LTPS TFT substrate as claimed in claim 1, wherein the first gate insulating layer and the second gate insulating layer are made of silicon nitride or silicon oxide; the first gate and the second gate are made of molybdenum; the interlayer insulating layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the source and the drain are a molybdenum/aluminum/molybdenum laminant layer. 5. The manufacturing method for LTPS TFT substrate as claimed in claim 1, wherein the ends of the second gate extend beyond the both ends of the first gate by 1-2 μm, respectively. 6. A manufacturing method for low temperature polysilicon (LTPS) thin film transistor (TFT) substrate, which comprises: Step 1: providing a substrate, and depositing a buffer layer on the substrate;Step 2: depositing a first metal layer on the buffer layer, patterning the first metal layer to obtain a first gate, and depositing a first gate insulating layer on the first gate;Step 3: depositing an amorphous silicon (a-Si) layer on the first gate insulating layer, performing dehydrogenation treatment on the a-Si layer, performing a crystallization process to turn the a-Si layer into a polysilicon layer, and patterning the polysilicon layer to obtain an island-shape polysilicon layer above the corresponding first gate;Step 4: coating a photo-resist on the island-shape polysilicon layer and performing exposure and development on the photo-resist to form a photo-resist layer;using the photo-resist layer as a masking layer to perform ion implantation on both sides of the island-shape polysilicon layer to form N-type heavily doped (N+) areas on both sides of the island-shape polysilicon layer and an undoped area between the N type heavily doped N+ areas, and then peeling the photo-resist layer off, wherein the undoped area having a width greater than the a width of the first gate;Step 5: depositing a second gate insulating layer on the island-shape polysilicon gate layer, depositing a second metal layer on the second gate insulating layer, and patterning the second metal layer to obtain a corresponding second gate above the undoped area, and the second gate insulating layer having a thickness greater than a thickness of the first gate insulating layer, wherein the second gate having a width equal to a width of the undoped area, and both ends of the second gate extending beyond the both ends of the first gate so that a portion of the undoped area covered by both the first gate and the second gate forms a groove area with a strong electric field, and the portion of the undoped area covered only by the second gate forming a low electric field area;Step 6: depositing an interlayer insulating layer between the second gate insulting layer and the second gate; performing a lithography process to form vias on the interlayer insulating layer and the second gate insulating layer over the N+ areas on both sides of the island-shape polysilicon layer; andStep 7: depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain source/drain, the source/drain contacting through the vias the N-type heavily doped N+ areas on the both sides of the island-shape polysilicon layer. 7. The manufacturing method for LTPS TFT substrate as claimed in claim 6, wherein in Step 1, the substrate is a glass substrate; the buffer layer is a laminant layer with a silicon nitride layer and a silicon oxide layer; a thickness of the silicon nitride layer is 40-100 nm; a thickness of the silicon oxide layer is 100-200 nm. 8. The manufacturing method for LTPS TFT substrate as claimed in claim 6, wherein in Step 2, a thickness of the a-Si layer is 40-60 nm; the crystallization process is an excimer laser annealing or solid-phase crystallization process. 9. The manufacturing method for LTPS TFT substrate as claimed in claim 6, wherein the first gate insulating layer and the second gate insulating layer are made of silicon nitride or silicon oxide; the first gate and the second gate are made of molybdenum; the interlayer insulating layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the source/drain is a molybdenum/aluminum/molybdenum laminant layer. 10. The manufacturing method for LTPS TFT substrate as claimed in claim 6, wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer by 200-500 Å; respective ends of the second gate extend beyond the both ends of the first gate by 1-2 μm, respectively. 11. A manufacturing method for low temperature polysilicon (LTPS) thin film transistor (TFT) substrate, which comprises: Step 1: providing a substrate, and depositing a buffer layer on the substrate;Step 2: depositing a first metal layer on the buffer layer, patterning the first metal layer to obtain a first gate, and depositing a first gate insulating layer on the first gate;Step 3: depositing an amorphous silicon (a-Si) layer on the first gate insulating layer, performing dehydrogenation treatment on the a-Si layer, performing a crystallization process to turn the a-Si layer into a polysilicon layer, and patterning the polysilicon layer to obtain an island-shape polysilicon layer above the corresponding first gate;Step 4: coating a photo-resist on the island-shape polysilicon layer and performing exposure and development on the photo-resist to form a photo-resist layer; using the photo-resist layer as a masking layer to perform ion implantation on both sides of the island-shape polysilicon layer to form N-type heavily doped (N+) areas on both sides of the island-shape polysilicon layer and an undoped area between the two N+ areas, and then peeling the photo-resist layer off, wherein the undoped area has a width greater than a width of the first gate;Step 5: depositing a second gate insulating layer on the island-shape polysilicon gate layer, depositing a second metal layer on the second gate insulating layer, and patterning the second metal layer to obtain a corresponding second gate above the undoped area, and the second gate insulating layer having a thickness greater than a thickness of the first gate insulating layer, wherein the second gate having a width equal to the width of the undoped area, and both ends of the second gate extending beyond both ends of the first gate so that a portion of the undoped area covered by both the first gate and the second gate forms a groove area with a strong electric field, and the portion of the undoped area covered only by the second gate forms a low electric field area;Step 6: depositing an interlayer insulating layer between the second gate insulting layer and the second gate; performing a lithography process to form vias on the interlayer insulating layer and the second gate insulating layer over the N-type heavily doped N+ areas on both sides of the island-shape polysilicon layer; andStep 7: depositing a third metal layer on the interlayer insulating layer, patterning the third metal layer to obtain a source and a drain, the source and the drain contacting through the vias the N-type heavily doped N+ areas on both sides of the island-shape polysilicon layer;wherein in Step 1, the substrate is a glass substrate; the buffer layer is a composite layer with a silicon nitride layer and a silicon oxide layer; the thickness of the silicon nitride layer is 40-100 nm; the thickness of the silicon oxide layer is 100-200 nm;wherein in Step 2, the thickness of the a-Si layer is 40-60 nm; the crystallization process is an excimer laser annealing or solid-phase crystallization process;wherein the first gate insulating layer and the second gate insulating layer are made of silicon nitride or silicon oxide; the first gate and the second gate are made of molybdenum; the interlayer insulating layer is a silicon nitride layer, a silicon oxide layer, or a combination of the two; the source and the drain are a molybdenum/aluminum/molybdenum laminant layer;wherein a thickness of the second gate insulating layer is greater than a thickness of the first gate insulating layer by 200-500 Å; ends of the second gate extend beyond both ends of the first gate by 1-2 μm, respectively.
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