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An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains

An Ultra Thin Body and Box (UTBB) fully depleted silicon on insulator (FDSOI) field effect transistor (FET) employing a split gate topology is provided. A gate dielectric layer is disposed beneath a gate structure and in contact with a channel layer of the device. The gate dielectric layer contains two portions, a thin portion and a thick portion. The thin portion is arranged and configured to reduce a trans-conductance of the device, while a thick portion is arranged and configured to increase the break down voltage of the device. The device further contains a bulk region that can be electrically connected to voltage source to provide control over the threshold voltage of the device.

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1. A semiconductor device, comprising: a source region disposed above a substrate layer;a drain region disposed above the substrate layer and laterally spaced apart from the source region;a channel layer disposed above the substrate layer and disposed between the source region and the drain region;a

1. A semiconductor device, comprising: a source region disposed above a substrate layer;a drain region disposed above the substrate layer and laterally spaced apart from the source region;a channel layer disposed above the substrate layer and disposed between the source region and the drain region;a gate electrode disposed above the channel layer and laterally between the source region and the drain region; anda gate dielectric region disposed between the gate electrode and the channel layer, the gate dielectric region including a first portion and a second portion, wherein a thickness of the second portion is greater than a thickness of the first portion,wherein the first portion of the gate dielectric region is disposed relatively proximally to the source region, and wherein the second portion of the gate dielectric region is disposed relatively proximally to the drain region, andwherein the first portion and the second portion of the gate dielectric region are formed from different dielectric materials. 2. The semiconductor device of claim 1, wherein the first portion of the gate dielectric region is adjacent to, and in contact with, the second portion of the gate dielectric region. 3. The semiconductor device of claim 1, wherein the channel layer is disposed above and in contact with a buried oxide (BOX) layer to form a fully depleted silicon-on-insulator (FDSOI) device. 4. The semiconductor device of claim 1, further comprising: a spacer layer comprising a first portion and a second portion, the first portion of the spacer layer disposed between the gate dielectric region and the source region, and the second portion of the spacer layer disposed between the gate dielectric region and the drain region. 5. A semiconductor device, comprising: a source region disposed above a substrate layer;a drain region disposed above the substrate layer and laterally spaced apart from the source region;a channel layer disposed above the substrate layer and disposed between the source region and the drain region;a gate electrode disposed above the channel layer and laterally between the source region and the drain region; anda gate dielectric region disposed between the gate electrode and the channel layer, the gate dielectric region including a first portion and a second portion, wherein a thickness of the second portion is greater than a thickness of the first portion, andwherein the source region, the drain region, and the channel layer are disposed above a split well layer. 6. The semiconductor device of claim 5, wherein the split well layer includes a first portion with a first doping polarity and a second portion with a second doping polarity, wherein the first doping polarity and the second doping polarity are complementary. 7. The semiconductor device of claim 6, wherein a threshold voltage of the semiconductor device is adjusted by applying a voltage to the first portion of the split well layer relative to the second portion of the split well layer. 8. The semiconductor device of claim 5, wherein the split well layer includes a first portion that is doped N-type, and a second portion that is doped P-type, wherein a threshold voltage of the semiconductor device is adjusted by applying a voltage to the first portion of the split well layer relative to the second portion of the split well layer. 9. The semiconductor device of claim 5, wherein the first portion of the gate dielectric region is disposed relatively proximally to the source region, and wherein the second portion of the gate dielectric region is disposed relatively proximally to the drain region. 10. The semiconductor device of claim 5, wherein the first portion of the gate dielectric region is adjacent to, and in contact with, the second portion of the gate dielectric region. 11. The semiconductor device of claim 5, wherein the channel layer is disposed above and in contact with a buried oxide (BOX) layer to form a fully depleted silicon-on-insulator (FDSOI) device. 12. The semiconductor device of claim 5, further comprising: a spacer layer comprising a first portion and a second portion, the first portion of the spacer layer disposed between the gate dielectric region and the source region, and the second portion of the spacer layer disposed between the gate dielectric region and the drain region. 13. A semiconductor device, comprising: a source region disposed above a substrate layer;a drain region disposed above the substrate layer and laterally spaced apart from the source region;a channel layer disposed above the substrate layer and disposed between the source region and the drain region;a gate electrode disposed above the channel layer and laterally between the source region and the drain region; anda gate dielectric region disposed between the gate electrode and the channel layer, the gate dielectric region including a first portion configured to have a first breakdown voltage and a second portion configured to have a second breakdown voltage, wherein the second breakdown voltage is greater than the first breakdown voltage,wherein the first portion of the gate dielectric region is disposed relatively proximally to the source region, and wherein the second portion of the gate dielectric region is disposed relatively proximally to the drain region, andwherein the first portion and the second portion of the gate dielectric region are formed from different dielectric materials. 14. The semiconductor device of claim 13, wherein the first portion of the gate dielectric region is adjacent to, and in contact with, the second portion of the gate dielectric region. 15. The semiconductor device of claim 14, wherein a thickness of the second portion is greater than a thickness of the first portion. 16. The semiconductor device of claim 15, wherein a threshold voltage of the semiconductor device is substantially determined by the thickness of the first portion. 17. The semiconductor device of claim 13, wherein the channel layer is disposed above and in contact with a buried oxide (BOX) layer to form a fully depleted silicon-on-insulator (FDSOI) device. 18. A semiconductor device, comprising: a source region disposed above a substrate layer;a drain region disposed above the substrate layer and laterally spaced apart from the source region;a channel layer disposed above the substrate layer and disposed between the source region and the drain region;a gate electrode disposed above the channel layer and laterally between the source region and the drain region; anda gate dielectric region disposed between the gate electrode and the channel layer, the gate dielectric region including a first portion configured to have a first breakdown voltage and a second portion configured to have a second breakdown voltage, wherein the second breakdown voltage is greater than the first breakdown voltage, andwherein the source region, the drain region, and the channel layer are disposed above a split well layer, wherein the split well layer includes a first portion with a first doping polarity and a second portion with a second doping polarity, wherein the first doping polarity and the second doping polarity are complementary. 19. The semiconductor device of claim 18, wherein the threshold voltage of the semiconductor device is adjusted by applying a voltage to the first portion of the split. 20. The semiconductor device of claim 18, wherein the first portion of the gate dielectric region is disposed relatively proximally to the source region, and wherein the second portion of the gate dielectric region is disposed relatively proximally to the drain region. 21. The semiconductor device of claim 18, wherein the first portion of the gate dielectric region is adjacent to, and in contact with, the second portion of the gate dielectric region.