$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

Improving Short Channel Effects by Reformed U-Channel UTBB FD SOI MOSFET: A Feasible Scaled Device

Silicon, v.14 no.3, 2022년, pp.1013 - 1022  

Ghassemi, Moslem ,  Orouji, Ali A.

초록이 없습니다.

참고문헌 (33)

  1. IEEE Electron Device Lett J Chen 32 1346 2011 10.1109/LED.2011.2162813 Chen J, Luo J, Wu Q, Chai Z, Yu T, Dong Y, Wang X (2011) A tunnel diode body contact structure to suppress the floating-body effect in partially depleted SOI MOSFETs. IEEE Electron Device Lett 32:1346-1348 

  2. 10.1016/j.spmi.2014.04.010 Orouji AA, Anvarifard MK (2014) Novel reduced body charge technique in reliable nanoscale SOI MOSFETs for suppressing the kink effect. Super lattices Microstruct 72:111-125 

  3. Nuclear Instrum Methods Phys Res J Chen 272 128 2012 10.1016/j.nimb.2011.01.048 Chen J, Luo J, Wu Q, Chai Z, Huang X, Wei X, Wang X (2012) Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs. Nuclear Instrum Methods Phys Res 272:128-131 

  4. 10.1016/j.mee.2005.11.002 Ali A. Orouji, M. Jagadesh Kumar (2006) A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain,” Microelectronic Engineering, pp 409-414 

  5. Proc IEEE L Chang 9 1860 2003 10.1109/JPROC.2003.818336 Chang L, Choi Y-K, Ha D, Ranade P, Xiong S, Bokor J, Hu C, King T-J (2003) Extremely scaled silicon Nano-CMOS devices. Proc IEEE 9:1860-1873 

  6. Mater Sci Semicond Process A Abbasi 16 1821 2013 10.1016/j.mssp.2013.06.022 Abbasi A, Orouji AA (2013) A silicon/indium arsenide source structure to suppress the parasitic bipolar-induced breakdown effect in SOI MOSFETs. Mater Sci Semicond Process 16:1821-1827 

  7. 10.1109/SOI.2002.1044462 Min BW, Kang L, Wu D, Caffo D, Hayden J, Mendicino MA (2002) Reduction of hysteretic propagation delay with less performance degradation by novel body contact in PD SOI application. IEEE Int SOI Conf:169-170 

  8. 10.1016/j.spmi.2016.11.022 Zareiee M, Orouji AA (2016) Superior electrical characteristics of novel Nanoscale MOSFET with embedded tunnel diode,” Super-lattices and Microstructures 101:57-67 

  9. 10.1109/ICSICT.2006.306139 Cao J, Li D, Ke W, Sun L, Han R, Zhang S (2006) T-shaped body silicon-on-insulator (SOI) MOSFET. IEEE:1293-1295 

  10. 10.1109/LED.2011.2106755 Chieh-Lin W, Chikuang Y, Shichijo H, Kenneth KO 2011 I-gate body-tied silicon-on-insulator MOSFETs with improved high-frequency performance. IEEE Electron Device Lett:443-445 

  11. 10.1016/j.spmi.2017.09.042 Ramezani Z, Orouji AA 2017 Dual gate tunneling field effect transistors based on MOSFETs: a 2-D analytical approach. Superlattices Microstruc 113:41-56 

  12. 10.1007/s12633-019-00358-4 Aghaeipour Z, Naderi A 2019 Embedding two P+ pockets in the buried oxide of Nano silicon on insulator MOSFETs: controlled Short Channel effects and electric field. Silicon 12:26111-2618 

  13. 10.1016/j.aeue.2018.01.001 Naderi A, Heirani F (2018) A novel SOI-MESFET with symmetrical oxide boxes at both sides of gate and extended drift region into the buried oxide. Int J Electron Commun:91-98 

  14. Microelectron J K Rajendran 32 631 2001 10.1016/S0026-2692(01)00047-7 Rajendran K, Schoenmaker W (2001) Modeling of minimum surface potential and sub-threshold swing for grooved-gate MOSFETs. Microelectron J 32:631-639 

  15. 10.1109/JEDS.2018.2809587 Ramachandran Muralidhar, Robert H. Dennard,Takashi Ando, Isaac Lauer, Terence ook, “Advanced FDSOI Device Design: The U-Channel Device for 7 nm Node and Beyond,” Electron Dev Soc, pp. 551-556, 2018, 6 

  16. 10.1016/j.spmi.2017.07.043 Lenka AS, Mishra S, Mishra S, Bhanja U, Mishra GP (2017) An extensive investigation of work function modulated trapezoidal recessed channel MOSFET. Superlatt Microstruct:878-888 

  17. Solid State Electron B Kazemi Esfeh 117 130 2016 10.1016/j.sse.2015.11.020 Kazemi Esfeh B, Kilchytska V, Barral V, Planes N, Haond M, Flandre D, Raskin JP (2016) Assessment of 28 nm UTBB FD-SOI technology platform for RF applications: figures of merit and effect of parasitic elements. Solid State Electron 117:130-137 

  18. IEEE Trans Electron Dev AK Ben 61 722 2014 10.1109/TED.2014.2302685 Ben AK (2014) Performance of SOI CMOS technology on commercial 200-mm enhanced signal integrity high resistivity SOI substrate. IEEE Trans Electron Dev 61:722-728 

  19. IEEE Trans Electron Dev T Skotnicki 55 96 2008 10.1109/TED.2007.911338 Skotnicki T, Fenouillet-Beranger C, Gallon C, Boeuf F, Monfray S, Payet F, Pouydebasque A, Szczap M, Farcy A, Arnaud F, Clerc S, Sellier M, Cathignol A, Schoellkopf J-P, Perea E, Ferrant R, Mingam H (2008) Innovative materials, devices, and CMOS technologies for low-power mobile multimedia. IEEE Trans Electron Dev 55:96-130 

  20. IEEE Electron Dev Lett Y-K Choi 21 254 2000 10.1109/55.841313 Choi Y-K, Asano K, Lindert N, Subramanian V, King T-J, Bokor J, Hu C (2000) Ultra-thin-body SOI MOSFET for deep-sub-tenth. IEEE Electron Dev Lett 21:254-255 

  21. 10.1109/TED.2011.2172993 Arshad MoMd, Raskin J-P, Kilchytska V, Andrieu F, Scheiblin P, Faynot O, Flandre D (2012) Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs. IEEE Trans Electron Dev:247-251 

  22. 10.1109/ISPSD.2015.7123392 Litty A, Ortolland S, Golanski D, Cristoloveanu S (2015) Optimization of a high-voltage MOSFET in ultra-thin 14nm FDSOI Technology. Proceedings of the 27th International Symposium on Power Semiconductor Devices & IC's, pp 73-76 

  23. Solid State Electron S Burignat 54 213 2010 10.1016/j.sse.2009.12.021 Burignat S, Flandre D, Md Arshad MK, Kilchytska V, Andrieu F, Faynot O, Raskin J-P (2010) Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and un-doped channel. Solid State Electron 54:213-219 

  24. Sugii N, Tsuchiya R, Ishigaki T, Morita Y, Yoshimoto H, Torii K, Kimura S (2008) Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: finding a way to further reduce variation. IEEE Electron Dev Meeting:1-4 

  25. IEEE Electron Device Letters T Ohtou 28 740 2007 10.1109/LED.2007.901276 Ohtou T, Sugii N, Hiramoto T (2007) Impact of parameter variations and random dopant fluctuations on short-channel fully depleted SOI MOSFETs with extremely thin BOX. IEEE Electron Device Letters 28:740-742 

  26. 10.1109/16.987118 Kim S-D, Park C-M, Woo JCS (2002) Advanced model and analysis of series resistance for CMOS scaling into nanometer regime-part II quantitative analysis. IEEE Trans Electron Dev:467-472 

  27. Doyle B, Arghavani R, Barlage D, Datta S, Doczy M, Kavalieros J, Murthy A, Chau R (2002) Transistor elements for 30 nm physical gate lengths and beyond. Intel Technol J Semiconduct Technol Manufact:42-54 

  28. 10.1109/IEDM.2002.1175829 Doris B, Ieong M, Kanarsky T, Zhang Y, Roy RA, Dokumaci O, Ren Z, Jamin F-F, Shi L, Natzle W, Huang H-J, Mezzapelle J, Mocuta A, Womack S, Gribelyuk M, Jones EC, Miller RJ, Philip Wong H-S, Haensch W (2002) Extreme scaling with ultra-thin Si channel MOSFETs. IEEE Electron Dev Meeting:267-270 

  29. J Appl Phys GD Wilk 89 5243 2001 10.1063/1.1361065 Wilk GD, Wallace RM, Anthony JM (2001) High-κ gate dielectrics: current status and materials properties considerations. J Appl Phys 89:5243-5275 

  30. 10.1109/INTERCON.2018.8526445 Trojman L, Vaca A (2018) Luis Miguel Procel, “on the parameter extraction of short channel UTBB FD SOI FET’s with high-κ metal gate and TCAD Modelling:1-4 

  31. Device Simulator Atlas User's Manual, Silvaco International Software, Santa Clara, USA, January (2017) Silvaco International, Santa Clara 〈www.silvaco.com〉 

  32. Solid State Electron MK Md Arshad 97 38 2014 10.1016/j.sse.2014.04.027 Md Arshad MK, Kilchytska V, Emam M, Andrieu F, Flandre D, Raskin J-P (2014) Effect of parasitic elements on UTBB FD SOI MOSFETs RF figures of merit. Solid State Electron 97:38-44 

  33. 10.1007/978-1-4757-2121-8 Colinge J-P (1991) Silicon-on-insulator technology: materials to VLSI. Kluwer Academic Publishers 

섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로