Multi-layer work function metal gates with similar gate thickness to achieve multi-Vt for vFETS
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/28
H01L-021/8234
H01L-027/088
H01L-027/092
H01L-021/8238
H01L-029/49
H01L-029/66
출원번호
US-0481012
(2017-04-06)
등록번호
US-10002791
(2018-06-19)
발명자
/ 주소
Bao, Ruqiang
Jagannathan, Hemanth
Jamison, Paul C.
Lee, ChoongHyun
출원인 / 주소
International Business Machines Corporation
대리인 / 주소
Tutunjian & Bitetto, P.C.
인용정보
피인용 횟수 :
0인용 특허 :
5
초록▼
A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four
A method is presented for forming a device having multiple field effect transistors (FETs) with each FET having a different work function. In particular, the method includes forming multiple microchips in which each FET has a different threshold voltage (Vt) or work-function. In one embodiment, four FETs are formed over a semiconductor substrate. Each FET has a source, drain and a gate electrode. Each gate electrode is processed independently to provide a substantially different threshold voltage.
대표청구항▼
1. A method for forming a device having multiple field effect transistors (FETs) with each FET having a different work function gate stack, the method comprising: forming first, second, third, and fourth FETs over a semiconductor substrate;forming an interfacial layer and a high-k dielectric layer o
1. A method for forming a device having multiple field effect transistors (FETs) with each FET having a different work function gate stack, the method comprising: forming first, second, third, and fourth FETs over a semiconductor substrate;forming an interfacial layer and a high-k dielectric layer over the first, second, third, and fourth FETs;forming a first work function conducting layer over the high-k dielectric layer;removing the first work function conducting layer from the third FET;depositing a second work function conducting layer;removing the first and second work function conducting layers from the second FET;depositing a third work function conducting layer;removing the first, second, and third work function conducting layers from the first FET;depositing a fourth work function conducting layer;depositing a sacrificial block layer and a sacrificial cap layer;removing the sacrificial block layer and the sacrificial cap layer from the first and second FETs;depositing a fifth work function conducting layer and a patterning cap layer;removing the patterning cap layer, the fifth work function conducting layer, and the sacrificial cap layer from the third and fourth FETs;removing the sacrificial block layer from the third and fourth FETs;depositing first and second conducting layers over the first, second, third, and fourth FETs;depositing a dummy fill material;recessing the dummy fill material;recessing remaining work function conducting layers from the first, second, third, and fourth FETs to expose a hard mask of each of the first, second, third, and fourth FETs;stripping the dummy fill material;depositing a dielectric layer up to a top surface of the hard mask of each of the first, second, third, and fourth FETs;recessing the dielectric layer and forming spacers;performing isolation patterning of the first, second, third, and fourth FETs for isolation FETs;depositing an insulator between the recesses formed by the isolation patterning; andetching to expose a top portion of a channel of each of the first, second, third, and fourth FETs. 2. The method of claim 1, wherein the first, second, third, and fourth work function conducting layers are titanium nitride (TiN) layers. 3. The method of claim 1, wherein the fifth work function conducting layer is an nFET work function metal. 4. The method of claim 3, wherein the nFET work function metal is one of titanium(Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or any combination of Ti and Al alloys. 5. The method of claim 1, wherein the patterning cap layer is a TiN layer. 6. The method of claim 1, wherein the first conducting layer is a scavenging metal or metal alloy and the second conducting layer is metal nitride, metal carbide or pure metals. 7. The method of claim 6, wherein a scavenging metal or metal alloy is one of titanium(Ti), aluminum (Al), titanium aluminum (TiAl), titanium aluminum carbon (TiAlC), or any combination of Ti and Al alloys; wherein the metal nitride is TiN, AlN; wherein the metal carbide is TiC, WC, AlC, TaC; and wherein the pure metal is Co, Al, Ti, Ru, and W. 8. The method of claim 1, wherein the dummy fill material is an organic planarization layer (OPL). 9. The method of claim 1, further comprising forming source/drain regions over the channel of each of the first, second, third, and fourth FETs and further comprising forming contacts to each of the source/drain regions over each channel. 10. The method of claim 1, wherein a difference in thickness between the first, second, third, fourth, and fifth work function conducting layers is less than 2 nm.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (5)
Edge, Lisa F.; Jagannathan, Hemanth; Haran, Balasubramanian S., Integration of multiple threshold voltage devices for complementary metal oxide semiconductor using full metal gate.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.