보고서 정보
주관연구기관 |
서울대학교 Seoul National University |
연구책임자 |
김형준
|
참여연구자 |
황철성
,
강상열
,
박재후
,
권오성
,
노상용
,
조금석
,
김범석
,
조문주
,
오진호
,
김성근
,
박태주
,
엄다일
,
박우영
,
정두석
,
이상운
,
최병준
,
허재영
,
서민하
,
심준섭
,
홍석훈
,
서한석
,
임정혁
|
발행국가 | 대한민국 |
언어 |
한국어
|
발행년월 | 2005-06 |
과제시작연도 |
2004 |
주관부처 |
과학기술부 |
사업 관리 기관 |
한국과학재단 Korea Science and Engineering Foundtion |
등록번호 |
TRKO200500066701 |
과제고유번호 |
1350019499 |
사업명 |
국가지정연구실사업 |
DB 구축일자 |
2013-04-18
|
초록
▼
1. 고/강유전막을 이용한 미소커패시터 제조기술 확보-BST MOCVD 공정 및 열처리 공정개발 : $T_{ox}$ $5.5{\AA}$, $\varepsilon_{\gamma}$=250, J=1$\times$$10^{-8}$A/$cm^2$ at $\pm$1V-BSTON sputter 공정 개발 $T_{ox}$ $5.5{\AA}$, $\varepsil
1. 고/강유전막을 이용한 미소커패시터 제조기술 확보-BST MOCVD 공정 및 열처리 공정개발 : $T_{ox}$ $5.5{\AA}$, $\varepsilon_{\gamma}$=250, J=1$\times$$10^{-8}$A/$cm^2$ at $\pm$1V-BSTON sputter 공정 개발 $T_{ox}$ $5.5{\AA}$, $\varepsilon_{\gamma}$=400-Perovskite $Pb(Mg_{1/3}Nb_{2/3})O_{3} -PbTiO_3$ [PMNT]박막 공정 개발 : $\varepsilon_{\gamma}$=1650, thickness $2200{\AA}$-확산방지막 증착 기술연구 : $TiCL_3$ $AlCl_3$ 등의 Cl계 CVD소스를 이용한 증착조건 확립 및 증착거동 연구수행.-STO ALD 공정 확보 : $T_{ox}$<0.8nm, J<2${\times}10^{-6}A/cm^{2}$ @${\pm}1V$, thickness&composition step coverage>$95\%$ @aspect ratio 8.-증착온도 $450^{circ}C$의 저온 PZT MOCVD 공정확보 : 박막두께 70-80nm, 2P.: $45{\mu}C/cm^2$, fatigue: $90\%(10^{10} cycle)$2. 고유전 MOSCAP 제조기술확보-MOSCAP용 STO ALD ; C 함유량 < 4$\%$, $T_{ox}$ < 4nm, J < $10^{-9}A/cm^2$-ALD/CVD $HfO_2$ MOSCAP 및 MOSFETs;$T_{ox}$ <$15{\AA}$, $D_{it}$$4{\times}10^{10}$ $cm^{-2}eV^{-1}$, translator 제작 mobility > $68\%$ of $SiO_2$, Subthreshold swing <80mV/dec, channek 길이 $0.5{\mu}m$의 short-channel transistor 제작-La-based oxide MOSCAP; C함유랭 <$1\%$ CET $11.6{\AA}$확보3. CVD/ALD Ru 전극 박막 공정의 개발-RU 박막 위에 $RuO_2$를 증착하고 이를 환원함으로써, rugged한 RU 박막을 얻는 데 성공-수소열처리를 통한 Ru/TiN 계면의 열적안정성 향상.-Pt doping을 통해 열처리 시 grain size 증가량을 $16\%$ 이내로 억제.-TiN과 $Ta_2O_5$ 위에서의 $Ru-RuO_2$ 박막의 증착거동 규명.-Ru 박막의 selectivity 특성 이해 및 플라즈마 처리를 통해 TiN 표면에서의 Ru 핵생성 특성 향상.-PEALD 법을 이용하여 Ru 박막의 공정 윈도우 확보 : RMS roughness < $5{\AA}$, sheet resistance uniformity < $2\%$ @ 8 inch wafer, step coverage > $90\%$, contact hole, aspect ratio $\sim$ 8.4. MIS, MIM 구조의 전기적 분석 이론 확립 및 각 소자로의 적용-DLTS, small-pulse DLTS, conductance method를 이용한 $Al_2O_3, Al_2O_3/HfO_2$ bi-layer, ALD $HfO_2$의 열처리, 산화제의 종류, 플라즈마 처리에 따른 $D_{it}$ 변화 및 capture cross section 거동 연구.-Pt/$HfO_2$/Si의 구조에서의 전도 mechanism 분석으로 산화제 종류에 따른 trap level의 깊이 변화 관찰-Pt/BST/$IrO_2$ 캐패시터에서 포텐셜 분포 계산을 통한 비대칭적인 I-V 곡선의 원인 규명.-UV ozone처리에 따른 $Ta_2O_5$ 박막의 Pool-Frenkel 전도 mechanism 분석.
Abstract
▼
The final goal of the development is to establish the fabrication technology of the next-generation capacitor and MOSFETS. And its subordinate objects are the development of the chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology in high-k dielectrics, ferroelectrics, metal e
The final goal of the development is to establish the fabrication technology of the next-generation capacitor and MOSFETS. And its subordinate objects are the development of the chemical vapor deposition (CVD) or atomic layer deposition (ALD) technology in high-k dielectrics, ferroelectrics, metal electrodes and gate oxide, and the development of their unit process. Moreover, the establishment of electrical and structural analysis techniques about the fabricated devices is also in interest. For the dielectric materials of next-generation DRAM capacitor, $(Ba,Sr)TiO_3$ (BST) and $SrTiO_3$ (STO) were investigated in this project. The BST films deposited on contact-hole structures by MOCVD method showed critical problem of thickness and composition variation according to the position in contact-hole, which was inevitable in conventional MOCVD method. However, contact-hole structure showing conformal thickness and composition step coverage could be fabricated when dome-type chamber was used in the conditions of high dome wall temperature. It is well known that STO ALD process is very difficult with conventional metal organic precursors and $H_{2}O$ vapor. But in this project, we found that the bubbling temperature of $Sr(thd)_2$ was the key factor for STO ALD. More than $90\%$ of thickness and compositional step coverage were obtained over contact hole structure (hole size $0.13{\mu}m$, aspect ratio 8) by lowering the temperature below melting point of $Sr(thd)_2$. The fabricated MIM capacitors showed equivalent oxide thickness below 1nm and leakage current density below $10^{-6}A/cm^2$ @1V. Thin ($70{\sim}80\;nm$) PZT films were deposited by MOCVD at temperatures between 450 and $525^{\circ}C$ for applications to ferroelectric memory devices. The adoption of new Zr and Ti precursors with MMP-ligands and a dome-type CVD reactor resulted in self-regulation of Pb incorporation as low temperature as $475^{\circ}C$, which provides a great promise for the low temperature integration of the PZT capacitors with logic devices. Pb and Zr+Ti incorporation into the PZT film appeared to occur through a competitive adsorption mechanism on the surface, and this mechanism successfully explains the self-regulation behavior of the variations in the film composition. The PZT films grown at $475^{\circ}C$ showed a promising ferroelectric properties, such as a high remnant polarization ($P_r\;>\;30\;mC/cm^{2}\;at\;4V$) and a small coercive voltage (${\sim}\;0.6\;V\;at\;a\;V_{a}\;of\;4.5V$) and low voltage (${\sim}\;4V$) $P_r$ saturation behavior. The remaining $P_r$ value after the fatigue test of $10^3$ cycles was above $90\%$ of the initial value even with a simple Pt-top electrode. $HfO_2$ films using NME and $H_{2}O$ source showed good dielectric properties and thermal stability and $D_{it}$ due to $SiN_x$ layer formation during ALD.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.