It is necessary to scale down MOSFET devices to improve performance and reduce manufacturing cost. However the scaling-down is known to cause some deleterious effects known as short-channel effects. These effects must be reduced for normal operation of MOSFET devices. The RCAT (Recess-Channel-Array ...
It is necessary to scale down MOSFET devices to improve performance and reduce manufacturing cost. However the scaling-down is known to cause some deleterious effects known as short-channel effects. These effects must be reduced for normal operation of MOSFET devices. The RCAT (Recess-Channel-Array Transistor) structure was introduced by researchers to solve this problem. The RCAT structure, in effect, increases the channel length by incorporating a recessed channel array in the body of the MOSFET device. Thus, the RCAT structure is expected to be very effective in reducing the short-channel effects. In the thesis, the RCAT structure was investigated by MEDICI device simulation to improve the performance of an n-type MOSFET device with a 30 nm gate length and a 30 nm junction depth (gate length : junction depth = 1 : 1). The gate electrode with protruding pins formed a recessed channel array in the silicon body of the transistor. The number of pins, the depth and width the pins, and the distance or space between adjacent pins were used as experimental variables. Two types of silicon substrate, bulk and SOI, were considered in the investigation. In terms of the key results, the short-channel effects, particularly DIBL, were reduced with the RCAT structure. In the bulk silicon substrate, the improvement in DIBL was related to the increase in the number of pins used, although the ideal number of pins was two, as the effect changed only a little with more pins. Also, it was most effective when the depth of a pin was 5㎚ and the width was 5㎚. In the SOI substrate, it was most effective to prevent the short-channel effects when the number of pins was one, the pin depth was 20㎚, and the pin width was 20㎚. In effect, the single pin seemed to have acted as a recessed gate. Significantly, increasing the number of pins did not lead to improved device characteristics in the SOI substrate case. The effect of changing the distance between the pins, from 4nm to 16nm, was relatively small and therefore not conclusive. Over all, the RCAT structure was found to be more useful for the bulk MOSFET devices than the SOI MOSFET devices. On the negative side, the drain current was generally reduced with the recessed channel arrays, and further work is needed to increase the drain current.
It is necessary to scale down MOSFET devices to improve performance and reduce manufacturing cost. However the scaling-down is known to cause some deleterious effects known as short-channel effects. These effects must be reduced for normal operation of MOSFET devices. The RCAT (Recess-Channel-Array Transistor) structure was introduced by researchers to solve this problem. The RCAT structure, in effect, increases the channel length by incorporating a recessed channel array in the body of the MOSFET device. Thus, the RCAT structure is expected to be very effective in reducing the short-channel effects. In the thesis, the RCAT structure was investigated by MEDICI device simulation to improve the performance of an n-type MOSFET device with a 30 nm gate length and a 30 nm junction depth (gate length : junction depth = 1 : 1). The gate electrode with protruding pins formed a recessed channel array in the silicon body of the transistor. The number of pins, the depth and width the pins, and the distance or space between adjacent pins were used as experimental variables. Two types of silicon substrate, bulk and SOI, were considered in the investigation. In terms of the key results, the short-channel effects, particularly DIBL, were reduced with the RCAT structure. In the bulk silicon substrate, the improvement in DIBL was related to the increase in the number of pins used, although the ideal number of pins was two, as the effect changed only a little with more pins. Also, it was most effective when the depth of a pin was 5㎚ and the width was 5㎚. In the SOI substrate, it was most effective to prevent the short-channel effects when the number of pins was one, the pin depth was 20㎚, and the pin width was 20㎚. In effect, the single pin seemed to have acted as a recessed gate. Significantly, increasing the number of pins did not lead to improved device characteristics in the SOI substrate case. The effect of changing the distance between the pins, from 4nm to 16nm, was relatively small and therefore not conclusive. Over all, the RCAT structure was found to be more useful for the bulk MOSFET devices than the SOI MOSFET devices. On the negative side, the drain current was generally reduced with the recessed channel arrays, and further work is needed to increase the drain current.
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#RCAT Recess-Channel-Array Transistor
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