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NTIS 바로가기電子工學會論文誌. Journal of the Institute of Electronics Engineers of Korea. SD, 반도체, v.38 no.4 = no.286, 2001년, pp.251 - 265
김영희 (창원대학교 전자공학과) , 김광현 (포항공과대학교 전자전기공학과) , 박홍준 (포항공과대학교 전자전기공학과) , 위재경 (현대전자 메모리개발연구소) , 최진혁 (현대전자 메모리개발연구소)
As the device scaling proceeds, the operating voltage(VDD) of giga-bit DRAMs is expected to be reduced to 1.5V or down, fir improving the device reliability and reducing the power dissipation. Therefore the low-voltage circuit design techniques are required to implement giga-bit DRAMs. In this work,...
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