최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기전기학회논문지. The transactions of the Korean Institute of Electrical Engineers. D / D, 시스템 및 제어부문, v.50 no.10, 2001년, pp.479 - 485
우영신 (고려대 공과학과) , 장영민 (고려대 공과학과) , 성만영 (고려대 공과학과)
In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase differ...
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
Y. Sumi, K. Syoubu, S. Obote, Y. Fukui, Y. Itoh, 'PLL frequency synthesizer with multi-phase detector', IEICE Trans.Fundamentals, vol. E82-A, no. 3, pp.431-435, March, 1999
K. M. Ware. Hae-Seung Lee, C. G. Sodini, 'A 200-MHz CMOS phase-locked loop with dual phase detectors', IEEE J.of Solid State Circuits, vol.24, no. 6, pp.1560-1568, Dec., 1989
A. Heiman, Y. Bar-Ness, 'Optimal design of PLL with two separate phase detectors' IEEE Trans.Commun., vol.com-29, no. 2, pp.92-100 Feb., 1981
Harufusa Kondoh, Hiromi Notani, Tsutomu Yoshimura, Hiroshi Shibata, Yoshio Matsuda, 'A 1.5V 250MHz to 3.0V 622MHz operation CMOS phase-locked loop with precharge type phase frequency detector', IEICE Trans.Electron., Vol. E78C, no. 4, pp.381-388, April, 1995
Hiroyasu Yoshizawa, Kenji Taniguchi, Hiroyuki Shirahama, Kenichi Nakashi, 'A low power 622MHz CMOS phase-locked loop with source coupled VCO and dynamic PFD', IEICE Trans.Fundamentals, vol. E80, no. 6, pp.1015-1020, June, 1997
Won-Hyo Lee, Sung-Dae Lee, Jun-Dong Cho, 'A high-speed,low-power phase frequency detector and charge-pump circuits for high frequency phase-locked loops', IEICE Trans. Fundamentals, vol. E82-A, no. 11, pp. 2514-2520, Nov., 1999
Henrik O. Johansson, A simple precharged CMOS phase frequency detector, IEEE J.of Solid State Circuits, vol. 33, no. 2, pp.295-299, Feb., 1998.
Kwangho Yoon, Wonchan Kim, 'Charge pump boosting technique for power noise immune high-speed PLL implementation', Electronics Letters, vol. 34, no.15, pp.1445-1446 July, 1988
Sungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog-Kyoon Jeong, Yunho Choi, Hyung Kyu Lim, 'A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLL', IEEE J.of Solid State Circuits, vol. 32, no. 5, pp.691-700, May, 1997
M. Soyuer, R. G. Meyer, 'Frequency limitations of a conventional phase-frequency detector', IEEE J.of Solid State Circuits, vol. 25, no. 4, pp.1019-1022, Aug., 1990
※ AI-Helper는 부적절한 답변을 할 수 있습니다.