Oh, Chang-Woo
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Kim, Sung-Hwan
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Yeo, Kyoung-Hwan
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Kim, Sung-Min
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Kim, Min-Sang
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Choe, Jeong-Dong
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Kim, Dong-Won
(Device Research Team, R&D Center, Samsung Electronics Co.)
,
Park, Dong-Gun
(Device Research Team, R&D Center, Samsung Electronics Co.)
In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect im...
In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.
In this article, we evaluated the structural merits and the validity of a partially insulated MOSFET (PiFET) through the fabrication of prototype transistors and an 80 nm 512M DDR DRAM with partially-insulated cell array transistors (PiCATs). The PiFETs showed the outstanding short channel effect immunity and off-current characteristics over the conventional MOSFET, resulting from self-induced halo region, self-limiting SID shallow junction, and reduced junction area due to PiOX layer formation. The DRAM with PiCATs also showed excellent data retention time. Thus, the PiFET can be a promising alternative for ultimate scaling of planar MOSFET.
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가설 설정
Figure 11. The channel regions were flattened by optimizing 2nd epi-Si growth process. The PiCAT is formed on the 50 nm-thick Si and 46 nm-thick PiOX.
제안 방법
Then, the masking layers were removed by wet etch, followed by the Si epitaxial growth (Figure 4 (b)). For the device isolation and the PiOX layer formation, the conventional shallow trench isolation (STI) process including pad oxide/SiN mask deposition and trench etch was carried out. The SiGe layers were selectively removed using a specially formulated etchant[7].
As shown in the figures, the PiFET has self-limited S/D junctions owing to PiOXs and body-tied channel region. For those three types of structures, several simulations using TSUPREM4 and MEDICI were performed in order to investigate the scalability of PiFET and the role of PiOX.
In this work, we evaluate the structural advantages of the PiFET through the 2-D simulation and demonstrate its outstanding performance through the fabrication. As one of PiFET applications, we introduce a partially insulated cell array transistor (PiCAT) for high-density DRAM products and demonstrate the improved data retention time characteristics.
To evaluate the VTH controllability and the scalability of the fabricated PiFETs, the electrical characteristics of the bulk MOSFETs and the PiFETs for various gate lengths and LPi, the spacing between the PiOXs, were measured by using parameter analyzer, HP4156. The Ids-Vgs characteristics of the fabricated bulk MOSFETs and PiFETs with Lg =143 nm and LPi=LG, Lg =195 nm and Lpi=LG, and LG =152 nm and LPi=0.
대상 데이터
3. Simulation results for VTH roll-off characteristics of a bulk MOSFET, an SOI MOSFET, and PiFETs.
The channel regions were flattened by optimizing 2nd epi-Si growth process. The PiCAT is formed on the 50 nm-thick Si and 46 nm-thick PiOX. The silicon body thickness is controllable by epi-Si growth process.
성능/효과
5LG are shown in Figure 6 and their key parameters are summarized in Table 1. According to the results, as the gate length is smaller and the LPi is narrower, short channel effects are effectively suppressed and threshold voltages are dramatically increased in PiFETs with halo. And also, the PiFETs even without h시o s사leme have better SCE immunity than the bulk MOSFET and the lowest junction leakage currents among them.
These good performances mainly resulted from selfeinduced halo region, self、 limiting S/D shallow junction, and reduced junction area due to PiOX layer formation. From the fabrication of an 80 nm 512M DRAM with PiCAT, its manufacturability was confirmed and its better SCE immunity was reconfirmed. Thus, the PiFET structure is believed to be one of the most promising candidates as a low power and high performance transistor in the ultimate scaling region of planar MOSFET.
The LPi is defined as the spacing between the PiOX layers. From the results, it was confirmed that PiOX layers make self-limited shallow S/D junctions and selfe induced halo regions near the edges of PiOX layers during thermal process.
참고문헌 (7)
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