다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기
Journal of semiconductor technology and science, v.14 no.4, 2014년, pp.484 - 494
Kavala, Anil (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Bae, Woorham (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Kim, Sungwoo (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Hong, Gi-Moon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Chi, Hankyu (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Kim, Suhwan (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University) , Jeong, Deog-Kyoon (Inter-University Semiconductor Research Center (ISRC) and the School of Electrical and Computer Engineering, Seoul National University)
AI-Helper
We describe a digitally controlled oscillator (DCO) which compensates the frequency variations for process, voltage, and temperature (PVT) variations with an accuracy of
* AI 자동 식별 결과로 적합하지 않은 문장이 있을 수 있으니, 이용에 유의하시기 바랍니다.
T. Olsson and P. Nilsson, "A digitally controlled PLL for SoC Applications," IEEE J. Solid-State Circuits, vol. 39, no. 5, pp. 451-460, May 2004.
D.-S. Kim, H. Song, T. Kim, S. Kim, and D.-K. Jeong , "A 0.3-1.4 GHz all-digital fractional-N PLL with adaptive loop gain controller," IEEE J. Solid-State Circuits, vol. 45, no. 11, pp. 2300-2311, Nov. 2010.
D.-H. Oh, D.-S. Kim, S. Kim, D.-K. Jeong, and W. Kim, "A 2.8Gb/s all-digital CDR with a 10b monotonic DCO," in Proc. IEEE Int. Solid-State Circuits Conf., pp.222-598, 2007.
H. Song, D.-S. Kim, D.-H. Oh, S. Kim, and D.-K. Jeong, "A 1.0-4.0-Gb/s all-digital CDR with 1.0-ps period resolution DCO and adaptive proportional gain control," IEEE J. Solid-State Circuits, vol. 46, no. 2, pp. 424-434, Feb. 2011.
C.-F. Tsai, W.-J. Li, P.-Y. Chen, Y.-Z. Lin, and S.- J. Chang, "On-chip reference oscillators with process, supply voltage and temperature compensation," in Proc. Int. Symp. Next- Generation Electronics, pp. 108-111, 2010, Taiwan.
X. Zhang and A. B. Apsel, "A low-power, processand- temperature -compensated ring oscillator with addition-based current source," IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 58, pp. 868-878, 2011.
R. Vijayaraghavan, S. K. Islam, M. R. Haider, and L. Zuo, "Wideband injection-locked frequency divider based on a process and temperature compensated ring oscillator," IET Circuits, Devices & Syst., vol. 3, pp. 259-267, 2009.
K. R. Lakshmikumar, V. Mukundagiri, and S. L. J. Gierkink, "A process and temperature compensated two-stage ring oscillator," in Proc. IEEE Custom Integr. Circuits Conf., pp. 691-694, 2007.
Y.-S. Park and W.-Y. Choi, "On-chip compensation of ring VCO oscillation frequency changes due to supply noise and process variation," IEEE Trans. Circuits Sys.-II, Exp. Briefs, vol. 59, no. 2, pp. 73-77, Feb. 2012.
M. Nekili, Y. Savaria, and G. Bois, "Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI," IEEE J. Solid-State Circuits, vol. 34, no. 1, pp. 80-84, Jan. 1999.
I. M. Filanovsky and A. Allam, "Mutual compensation of mobility and threshold voltage temperature effects with applications in CMOS circuits," IEEE Trans. on Circuits Syst. I, Fundamental Theory and Applications, vol. 48, no. 7, pp. 876-884, July 2001.
D.-H. Oh, K.-J. Choo, and D.-K. Jeong, "Phase-frequency detecting time-to-digital converter," IET Electronics Letters, vol. 45, no: 4, pp.201-202, Dec. 2009.
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
Copyright KISTI. All Rights Reserved.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.