[논문]High Performance p-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method

U, Myeonghun; Han, Young-Joon; Song, Sang-Hun; Cho, In-Tak; Lee, Jong-Ho; Kwon, Hyuck-In

doi:10.5573/jsts.2014.14.5.666

[국내논문] High Performance p-type SnO thin-film Transistor with SiOx Gate Insulator Deposited by Low-Temperature PECVD Method 원문보기

Journal of semiconductor technology and science, v.14 no.5, 2014년, pp.666 - 672

U, Myeonghun (School of Electrical and Electronics Engineering, Chung-Ang University) , Han, Young-Joon (School of Electrical and Electronics Engineering, Chung-Ang University) , Song, Sang-Hun (School of Electrical and Electronics Engineering, Chung-Ang University) , Cho, In-Tak (Department of Electrical and Computer Engineering, Seoul National University) , Lee, Jong-Ho (Department of Electrical and Computer Engineering, Seoul National University) , Kwon, Hyuck-In (School of Electrical and Electronics Engineering, Chung-Ang University)

Abstract ▼ AI-Helper

We have investigated the gate insulator effects on the electrical performance of p-type tin monoxide (SnO) thin-film transistors (TFTs). Various SnO TFTs are fabricated with different gate insulators of a thermal $SiO_2$, a plasma-enhanced chemical vapor deposition (PECVD) $SiO_x$, a $150^{\circ}C$-deposited PEVCD $SiO_x$, and a $300^{\circ}C$-deposited PECVD $SiO_x$. Among the devices, the one with the $150^{\circ}C$-deposited PEVCD $SiO_x$ exhibits the best electrical performance including a high field-effect mobility ($=4.86cm^2/Vs$), a small subthreshold swing (=0.7 V/decade), and a turn-on voltage around 0 (V). Based on the X-ray diffraction data and the localized-trap-states model, the reduced carrier concentration and the increased carrier mobility due to the small grain size of the SnO thin-film are considered as possible mechanisms, resulting in its high electrical performance.

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문제 정의

However, as of yet, no comparative report has been made on the effects of gate insulator in p-type SnO TFTs although the gate insulator can strongly affect the electrical performance of field-effect transistors including TFTs [7]. In this article, for the first time to the best of our knowledge, we comparatively investigate the effects of gate insulators on the electrical performance of p-type SnO TFTs. The experimental results show that it is very important to optimize the gate insulator to improve the electrical performance in p-type SnO TFTs.
In this article, we examine the effects of gate insulators on the electrical performance of p-type SnO TFTs. Various SnO TFTs are fabricated with different gate insulators of a thermal SiO₂, a PECVD SiN_x, a 150℃- deposited PEVCD SiO_x , and a 300℃-deposited PECVD SiO_x, and the device fabricated with a 150℃-deposited PEVCD SiO_x exhibits a much higher μ_FE, a smaller SS, and a more negatively shifted V_on compared to the devices with other gate insulators.

제안 방법

For the source/drain electrodes, a 50-nm-thick Ni was deposited at RT using an e-gun evaporator. All the layers in this work were patterned using shadow masks. The dielectric constants of the gate insulators are extracted to be 3.

대상 데이터

The experiments were performed on the p-type bottom gate SnO TFTs, where a heavily doped n-type silicon wafer was used as a substrate and a gate electrode. Four different dielectric layers including a thermal SiO₂ (= 116 nm), a SiN_x(= 110 nm) deposited by plasma-enhanced chemical vapor deposition (PECVD) at 250℃, and two SiO_xs deposited by PECVD at 150 (= 113 nm) and 300℃ (=99 nm) were incorporated into the devices as gate insulators.
Four different dielectric layers including a thermal SiO2 (= 116 nm), a SiNx (= 110 nm) deposited by plasma-enhanced chemical vapor deposition (PECVD) at 250℃, and two SiOxs deposited by PECVD at 150 (= 113 nm) and 300℃ (=99 nm) were incorporated into the devices as gate insulators.

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