[논문]반도체 프로브 공정에서의 2단계 계층적 생산 계획 방법 연구

방준영

doi:10.11627/jkise.2015.38.4.159

[국내논문] 반도체 프로브 공정에서의 2단계 계층적 생산 계획 방법 연구
Two-Level Hierarchical Production Planning for a Semiconductor Probing Facility 원문보기

Journal of Korean Society of Industrial and Systems Engineering = 한국산업경영시스템학회지, v.38 no.4, 2015년, pp.159 - 167

Abstract ▼ AI-Helper

We consider a wafer lot transfer/release planning problem from semiconductor wafer fabrication facilities to probing facilities with the objective of minimizing the deviation of workload and total tardiness of customers' orders. Due to the complexity of the considered problem, we propose a two-level hierarchical production planning method for the lot transfer problem between two parallel facilities to obtain an executable production plan and schedule. In the higher level, the solution for the reduced mathematical model with Lagrangian relaxation method can be regarded as a coarse good lot transfer/release plan with daily time bucket, and discrete-event simulation is performed to obtain detailed lot processing schedules at the machines with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated in the lower level. To evaluate the performance of the suggested planning method, we provide computational tests on the problems obtained from a set of real data and additional test scenarios in which the several levels of variations are added in the customers' demands. Results of computational tests showed that the proposed lot transfer/planning architecture generates executable plans within acceptable computational time in the real factories and the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.

주제어

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문제 정의

In this paper, we suggest a two-level hierarchical production planning method for a lot transfer problem between wafer fabrication facilities and wafer probing facilities to reduce the total tardiness of orders. In the higher level, a lot transfer plan is obtained by solving mathematical model, and schedules at the machines are obtained with a priority-rule-based scheduling method and the lot transfer/release plan is evaluated with the discrete-event simulation in the lower level.

가설 설정

3) The lower bound has not been decreased for a predetermined number of iterations (defined as B).

제안 방법

After transfer/release plan of wafer lots is obtained from the mixed integer programming (MIP) model, schedules at the workstations are obtained with a dispatching rule based scheduling method which is built in discrete-event simulation for the low level decision in the hierarchical production planning. In the discrete event simulation for detailed lot release schedule, More than one wafer probing facilities and several operation steps of workstations are modeled in detail based on the real factory information.
The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities. However, it may be more complicated and difficult to implement such a method in real situations.
To reduce the computational time to solve the problem [P] exactly, we propose the solution approach based on Lagrangian relaxation and sub-gradient optimization methods. In the algorithm, the problem is relaxed by dualizing the set of constraints with Lagrangian multipliers and then the relaxed problem is decomposed in two subproblems. Here, we show the following relaxed problem, [L.
Results of computational tests showed that the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities.
The performance of the lot scheduling algorithms suggested in this study is evaluated through simulation experiments. For the experiments, we generated problem instances based on data of a real wafer probing facility in top ranking semiconductor manufacturing company in Korea.
Results of computational tests showed that the total tardiness of orders can be reduced more effectively by using more sophisticated lot transfer methods, such as considering the due date and ready times of lots associated the same order with the mathematical formulation. The proposed method may be implemented for the problem of job assignment in back-end process such as the assignment of chips to be tested from assembly facilities to final test facilities. Also, the proposed method can be improved by considering the sequence dependent setup in the probing facilities.
For dynamic random access memory (DRAM) product, for example, the dies on the wafer is tested by writing a specific number on the die, reading the value from the die after the specified time, and verifying if the die can store the value properly. The test is performed under the predetermined temperature for each product type. The temperature range is 60~125°C, and the temperature is closely related to the working temperature of the final product, i.

대상 데이터

The performance of the lot scheduling algorithms suggested in this study is evaluated through simulation experiments. For the experiments, we generated problem instances based on data of a real wafer probing facility in top ranking semiconductor manufacturing company in Korea. The following summarize information of the real fab as well as wafers and orders used in the simulation model.

이론/모형

The performance of the suggested algorithm was compared with planning algorithm (named as REAL) which is used in the real probing facilities in the top rank semiconductor company in Korea. The performance index is shown as percentage of cost reduction from the resulting cost of REAL in the simulation test.

참고문헌 (20)

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원문보기 상세보기
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상세보기
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원문보기 상세보기
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상세보기
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상세보기

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용어 설명: PCR은 세균 특이성이 있는 primer를 이용하여 적은 수의 세균이 있을지라도 쉽게 검출할 수 있는 유용한 방법이며, 이를 이용하여 구강 내 치면세균막이나 타액에서 직접 세균을 검출할 수 있게 되었다[8].

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