This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromech...
This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.
This paper reports the results of a study on the optimization of the etching profile, which is an important factor in deep-reactive-ion etching (DRIE), i.e., dry etching. Dry etching is the key processing step necessary for the development of the Internet of Things (IoT) and various microelectromechanical sensors (MEMS). Large-area etching (open area > 20%) under a high-frequency (HF) condition with nonoptimized processing parameters results in damage to the etched sidewall. Therefore, in this study, optimization was performed under a low-frequency (LF) condition. The HF method, which is typically used for through-silicon via (TSV) technology, applies a high etch rate and cannot be easily adapted to processes sensitive to sidewall damage. The optimal etching profile was determined by controlling various parameters for the DRIE of a large Si wafer area (open area > 20%). The optimal processing condition was derived after establishing the correlations of etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and $SF_6$ gas flow rate. The processing-parameter-dependent results of the experiments performed for optimization of the etching profile in terms of etch rate, uniformity, and sidewall damage in the case of large Si area etching can be summarized as follows. When LF is applied, the platen power, coil power, and $SF_6$ should be low, whereas the run pressure has little effect on the etching performance. Under the optimal LF condition of 380 Hz, the platen power, coil power, and $SF_6$ were set at 115W, 3500W, and 700 sccm, respectively. In addition, the aforementioned standard recipe was applied as follows: run pressure of 4 Pa, $C_4F_8$ content of 400 sccm, and a gas exchange interval of $SF_6/C_4F_8=2s/3s$.
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문제 정의
This problem can be overcome by selecting processing conditions that minimize sidewall damage during DRIE etching [5-9]. As such, this study is aimed at determining the optimal processing parameters for minimizing the damage to the etched sidewall under a low-frequency (LF) condition of 380 kHz (RF generator) using a MACS Pegasus (Sumitomo Precision Products Co. Ltd, Japan).
Therefore, this study aimed to optimize the etching profile, an important factor in the DRIE process, which is a key processing step in the production of various MEMS structures. An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters.
This study aimed to optimize the etching profile, an important factor in the DRIE process, which is a key processing step in the production of various MEMS structures. An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters.
제안 방법
The aim of this study, therefore, was to analyze and subsequently reduce/eliminate the etch rate nonuniformity and sidewall damage tendencies that occur under large-area etching conditions (open area > 20%) for mass production applications.
An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters. The optimal processing condition was derived after establishing correlations of the etch rate, uniformity, and sidewall damage on a 6-in Si wafer to the parameters of coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate. Large-area etching (open area > 20%) under an HF condition with nonoptimized processing parameters results in damage to the etched sidewall.
An optimal etching profile for etching a large Si wafer area (open area > 20%) was determined by controlling various DRIE process parameters. The optimal processing condition was determined after establishing correlations of the etch rate, uniformity, and sidewall damage on a 6-in Si wafer to parameters such as the coil power, run pressure, platen power for passivation etching, and SF6 gas flow rate.
대상 데이터
Optimized photoresist (PR) masks and a SiO2 layer were used as etching masks in this study. Given that the etching method of the device used involves control of the plasma formation, etching duration and uniformity may vary according to the intensity of the platen power during the initial passivation.
이론/모형
Moreover, the etching-profile-related sidewall damage can lead to the formation of microbubbles in the flow path, resulting ultimately in its blockage and failure. Sidewall damage occurs during etching and is different from the scallop that inevitably results from the Bosch method. In previous studies [3], experiments were conducted with small sample-type parts.
참고문헌 (9)
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