Boukortt, Nour El Islam
(Department of Electrical Engineering, University of Mostaganem)
,
Hadri, Baghdad
(Department of Electrical Engineering, University of Mostaganem)
,
Caddemi, Alina
(DICIEAMA Department, University of Messina)
,
Crupi, Giovanni
(DICIEAMA Department, University of Messina)
,
Patane, Salvatore
(Dipartimento di Fisica e Scienze della Terra, University of Messina)
In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transc...
In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φm. As a consequence, the behavior of the leakage current improves with increased Φm. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.
In this paper, we present simulation results obtained using SILVACO TCAD tools for a 3-D silicon on insulator (SOI) n-FinFET structure with a gate length of 8 nm at 300K. The effects of variations of the device’s key electrical parameters, such as threshold voltage, subthreshold slope, transconductance, drain induced barrier lowering, oncurrent, leakage current and on/off current ratio are presented and analyzed. We will also describe some simulation results related to the influence of the gate work function variations on the considered structure. These variations have a direct impact on the electrical device characteristics. The results show that the threshold voltage decreases when we reduce the gate metal work function Φm. As a consequence, the behavior of the leakage current improves with increased Φm. Therefore, the short channel effects in real 3-D FinFET structures can reasonably be controlled and improved by proper adjustment of the gate metal work function.
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제안 방법
past thirty years. The goal is to integrate more components per unit area and, thus, improve circuit performance while lowering their manufacturing cost as predicted by "Moore’s Law";. Major semiconductor companies introduced the use of silicon on insulator (SOI) substrate in manufacturing microprocessors to minimize parasitic capacitances and to improve current drive, circuit speed and power consumption [1].
As with classic CMOS technology, the design of integrated circuits requires the availability of high performance and predictive compact models of these devices. In this work, we study the device structure SOI n-FinFET with an 8 nm gate length by keeping in mind either speed and power consumption as major targets. The region between the source and the drain of the analyzed device is covered by implementing the high-k gate dielectrics (Si3N4), which allows further miniaturization of electronic components.
이론/모형
The region between the source and the drain of the analyzed device is covered by implementing the high-k gate dielectrics (Si3N4), which allows further miniaturization of electronic components. In the simulation, the Lombardi constant voltage and temperature (CVT) and the Shockley-Read-Hall (SRH) models were considered. We also study the influence of variation of the gate work function on the most important parameters, such as threshold voltage (Vth), subthreshold slope (SS), transconductance (gm), drain induced barrier lowering (DIBL), on-current (Ion), leakage current (Ioff), and the on/off current ratio of nanoscale FinFETs.
In this work, we have used the numerical simulation tool Atlas Silvaco to construct, examine, and simulate a new SOI n-FinFET with a gate length of 8 nm. As indicated by the three-dimensional simulation results, we found that the short-channel effect (SCE) in SOI n-FinFET can be reasonably controlled and improved by proper adjustment of the metal gate work function.
The software package Silvaco-Atlas was used to construct, examine, and simulate the structure and characteristics of the FinFET device in three dimensions.
참고문헌 (13)
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