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NTIS 바로가기Journal of semiconductor technology and science, v.16 no.6, 2016년, pp.760 - 770
Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) , Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) , Yoo, Sang-Sun (Korea Advanced Institute of Science and Technology (KAIST)) , Kim, Joon-Tae (Department of Electronic Engineering, Konkuk University) , Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)
A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch...
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