[논문]A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC

Abbasizadeh, Hamed; Lee, Dong-Soo; Yoo, Sang-Sun; Kim, Joon-Tae; Lee, Kang-Yoon

doi:10.5573/jsts.2016.16.6.760

A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC 원문보기

Journal of semiconductor technology and science, v.16 no.6, 2016년, pp.760 - 770

Abbasizadeh, Hamed (College of Information and Communication Engineering, Sungkyunkwan University) , Lee, Dong-Soo (College of Information and Communication Engineering, Sungkyunkwan University) , Yoo, Sang-Sun (Korea Advanced Institute of Science and Technology (KAIST)) , Kim, Joon-Tae (Department of Electronic Engineering, Konkuk University) , Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University)

Abstract ▼ AI-Helper

A 12-bit 750 kS/s Dual-Sampling Successive Approximation Register Analog-to-Digital Converter (SAR ADC) technique with reduced Capacitive DAC (CDAC) is presented in this paper. By adopting the Adaptive Power Control (APC) technique for the two-stage latched type comparator and using bootstrap switch, power consumption can be reduced and overall system efficiency can be optimized. Bootstrapped switches also are used to enhance the sampling linearity at a high input frequency. The proposed SAR ADC reduces the average switching energy compared with conventional SAR ADC by adopting reduced the Most Significant Bit (MSB) cycling step with Dual-Sampling of the analog signal. This technique holds the signal at both comparator input asymmetrically in sample mode. Therefore, the MSB can be calculated without consuming any switching energy. The prototype SAR ADC was implemented in $0.18-{\mu}m$ CMOS technology and occupies $0.728mm^2$. The measurement results show the proposed ADC achieves an Effective Number-of-Bits (ENOB) of 10.73 at a sampling frequency of 750 kS/s and clock frequency of 25 MHz. It consumes only 0.13 mW from a 5.0-V supply and achieves the INL and DNL of +2.78/-2.45 LSB and +0.36/-0.73 LSB respectively, SINAD of 66.35 dB, and a Figures-of-Merit (FoM) of a 102 fJ/conversion-step.

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문제 정의

This paper describes how the SAR ADC operates by using a binary search algorithm so that the CDAC output converges on the input signal. It also explains the central aspect of the SAR ADC, the capacitive DAC, as well as the high-speed comparator.
This paper presents a power-efficient SAR ADC that combines several techniques to achieve low power design and speed requirements. First, the dual-sampling method is used to reduce the switching energy, reduce the total capacitance, and decrease the layout area and power consumption.

대상 데이터

This paper presents a 12-bit 25 MHz low power dual-sampling technique SAR ADC with reduced CDAC fabricated in 0.18-µm CMOS process technology.

이론/모형

46 bits with 374 kHz Nyquist input frequency. To compare the proposed ADC with other state-of-the-art SAR ADCs, the well-known figures-of-merit (FoM) equation is used [5].

성능/효과

0-V supply. It achieves FoM of 102 fJ/conversion-step, SINAD of 66.35 dB, and ENOB of 10.73. Actually, this technique is also applicable to SAR ADCs that operate at higher sampling frequencies.
Table 1 shows the signals’ state of the proposed comparator circuit. The simulation result shows that the proposed design exhibits a high resolution of 13bit and an ultra-low power consumption with 0.2mV offset and 2.4nsec output propagation delay.

참고문헌 (9)

S. Y. Baek, J. K. Lee, and S. T. Ryu, "An 88-dB max-SFDR 12-bit SAR ADC with speed-enhanced ADEC and dual registers," IEEE Trans. Circuits Syst. II, pp. 562-566, Sep. 2013.
A. Shrivastava, "12-bit non-calibrating noiseimmune redundant SAR ADC for System-on-achip," in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), pp. 1515-1518, May 2006.
B. Kim, L. Yan, J. Yoo, N. Cho, and H. J. Yoo, "An energy-efficient dual sampling SAR ADC with reduced capacitive DAC," IEEE Int. Symp. Circuits And Systems (ISCAS), pp. 972-975, May 2009.
S. I. Lim, J. W. Kim, K. S. Yoon, and S. M. Lee, "A 12-b asynchronous SAR type ADC for bio signal detection," Journal of Semiconductor Technology and Science, pp. 108-113, Apr. 2013.
R. H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Sel. Areas Commun., pp. 539-550, Apr. 1999.
Y. Siyu, Z. Hui, F. Wenhui, Y. Ting, and H. Zhiliang, "A low power 12-bit 200-kS/s SAR ADC with a differential time domain comparator," Journal of Semiconductors, pp. 035002-1-035002-6, Mar. 2011.
S. Lan, C. Yuan, Y. Y. H. Lam, and L. Siek, "An ultra low-power rail-to-rail comparator for ADC designs," MWSCAS, pp. 1-4, Aug. 2011.
A. D. Grasso, et. al. "Self-biased dual-path pushpull output buffer amplifier for LCD column drivers," IEEE Trans. Circuits Syst. I, pp. 663-670, Mar. 2014.
J. H. Wang, et. al. "A compact low-power high slew-rate rail-to-rail class-AB buffer amplifier for LCD driver ICs," EDSSC, IEEE Conf. On, pp. 397-400, Dec. 2007.

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A 12 bit 750 kS/s 0.13 mW Dual-sampling SAR ADC 원문보기

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