[논문]Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs

Um, Bu-Yong; Kim, Jong-Ryul; Kim, Sang-Hoon; Lee, Jae-Hoon; Cheon, Jimin; Choi, Jaehyuk; Chun, Jung-Hoon

doi:10.5573/jsts.2017.17.1.110

[국내논문] Design and Evaluation of a CMOS Image Sensor with Dual-CDS and Column-parallel SS-ADCs 원문보기

Journal of semiconductor technology and science, v.17 no.1, 2017년, pp.110 - 119

Um, Bu-Yong (College of Information & Communication Engineering, Sungkyunkwan University) , Kim, Jong-Ryul (College of Information & Communication Engineering, Sungkyunkwan University) , Kim, Sang-Hoon (College of Information & Communication Engineering, Sungkyunkwan University) , Lee, Jae-Hoon (School of Electronic Engineering, Kumoh National Institute of Technology) , Cheon, Jimin (School of Electronic Engineering, Kumoh National Institute of Technology) , Choi, Jaehyuk (College of Information & Communication Engineering, Sungkyunkwan University) , Chun, Jung-Hoon (College of Information & Communication Engineering, Sungkyunkwan University)

Abstract ▼ AI-Helper

This paper describes a CMOS image sensor (CIS) with dual correlated double sampling (CDS) and column-parallel analog-to-digital converter (ADC) and its measurement method using a field-programmable gate array (FPGA) integrated module. The CIS is composed of a $320{\times}240$ pixel array with $3.2{\mu}m{\times}3.2{\mu}m$ pixels and column-parallel 10-bit single-slope ADCs. It is fabricated in a $0.11-{\mu}m$ CIS process, and consumes 49.2 mW from 1.5 V and 3.3 V power supplies while operating at 6.25 MHz. The measured dynamic range is 53.72 dB, and the total and column fixed pattern noise in a dark condition are 0.10% and 0.029%. The maximum integral nonlinearity and the differential nonlinearity of the ADC are +1.15 / -1.74 LSB and +0.63 / -0.56 LSB, respectively.

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가설 설정

The control signal generation block has a finite state machine with 14 states in total, which are categorized and simplified in Fig. 4. Every control signal is synchronized with a main clock so that the operating frequency can be easily controlled. In the ‘Vsync’ state, the Vsync initializes the address of the FIFO between the FPGA and the USB microcontroller to read a new frame from the CIS.

제안 방법

In the column-parallel architecture, the simple single-slope ADC (SS-ADC) is preferred, because it can fit in a pixel pitch or two. In this paper, we demonstrate a dual-CDS CIS with column-parallel ADCs including double-data rate counters that utilize rising and falling edges of an operating clock to reduce power consumption [7]. We have also implemented a test system with a field-programmable gate array (FPGA) integrated module, which generates control signals for the CIS and converts sensor output signals to an image, performs systematic measurements, and quantify the image quality with proper performance metrics [8].

이론/모형

The performance metrics of the CIS were extracted from the captured images based on the Standard Mobile Imaging Architecture (SMIA) standard [8]. The dynamic range is an illumination range that an image sensor can represent in a frame; it is calculated as the full-scale deflection (FSD) divided by the standard deviation of the noise.

성능/효과

is the average of all the pixel outputs of the mean image. The measured dynamic range, the total FPN, and the column FPN are 53.72 dB, 0.10%, and 0.029%, respectively.
The FPGA module generates driving signals of the CIS and visualizes the output data as a digital image. The performance of the CIS was evaluated in compliance with the SMIA standard; the assessed dynamic range, total FPN, and column FPN in a dark condition were 53.72 dB, 0.10%, and 0.029%, respectively. The column-parallel ADCs were characterized automatically by utilizing a test column receiving a comparator input from the FPGA.

참고문헌 (13)

D. Lee, K. Cho, D, Kim, and G. Han, "Low-Noise In-Pixel Comparing Active Pixel Sensor Using Column-Level Single-Slope ADC," IEEE Trans. Electron Devices, vol. 55, no. 12, Dec. 2008.

상세보기
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D. Lee and G. Han, "High-speed, low-power correlated double sampling counter for columnparallel CMOS imagers," Electronics Letters, Vol. 43, No. 24, Nov. 2007.

상세보기
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상세보기
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