[논문]A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes

Jeong, Hocheol; Kang, Jaehyun; Lee, Kang-Yoon; Lee, Minjae

doi:10.5573/jsts.2017.17.3.370

[국내논문] A Simple Static Noise Margin Model of MOS CML Gate in CMOS Processes 원문보기

Journal of semiconductor technology and science, v.17 no.3, 2017년, pp.370 - 377

Jeong, Hocheol (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) , Kang, Jaehyun (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST)) , Lee, Kang-Yoon (College of Information and Communication Engineering, Sungkyunkwan University) , Lee, Minjae (School of Electrical Engineering and Computer Sciences, Gwangju Institute of Science and Technology (GIST))

Abstract ▼ AI-Helper

This paper presents a simple noise margin (NM) model of MOS current mode logic (MCML) gates especially in CMOS processes where a large device mismatch deteriorates logic reliability. Trade-offs between speed and logic reliability are discussed, and a simple yet accurate NM equation to capture process-dependent degradation is proposed. The proposed NM equation is verified for 130-nm, 110-nm, 65-nm, and 40-nm CMOS processes and has errors less than 4% for all cases.

Keyword

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가설 설정

Properties of a scaled CMOS process (a) NNM vs. A_V, (b) C_gs vs. A_V with low V_TH device in a 40-nm CMOS process.

제안 방법

In this paper, we propose a simple yet more accurate static NM model of MCML gates that reflects the NM degradation in deep submicron CMOS processes by introducing a process-dependent parameter that is close to around 0.5 with less than 4% NM error in recent technologies.
This paper provides a simple yet accurate NM equation of an MCML gate that captures process-dependent NM degradation in deep submicron CMOS processes. The proposed simple static NM modeling with a process-dependent correction constant of 0.

후속연구

5 results in a modeling error less than 4% of V_SW for modern CMOS processes. This model is expected to find a good use in pursuing high-speed and low-power MCML gate design with reliability in deep submicron CMOS processes.

참고문헌 (12)

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상세보기
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상세보기
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상세보기
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M. Alioto, et al, "Power-Delay-Area-Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic," Circuits and Systems I: Regular Papers, IEEE Transactions on , vol.54, no.9, pp.1916,1928, Sept. 2007.

상세보기
J. Lohstroh, "Static and dynamic noise margins of logic circuits," IEEE J, Solid-State Circuits, vol.14, no. 3, pp. 591-598, Jun. 1979.

상세보기
J. Lohstroh, E. Seevinck, and J. De Groot, "Worst-case static noise margin criteria for logic circuits and their mathematical equivalence," IEEE J. Solid-State Circuits, vol. SSC-18, no. 6, pp. 803-807, Dec. 1983.
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M. Lee, "A 20GHz variability-aware robust, high-speed and low-power MOS CML latch." IEICE Electronics Express, vol. 9, no. 14, pp. 1214-1220, July 2012.

상세보기
B. Razavi, Design of analog CMOS integrated circuits. New York: McGraw-Hill, 2001, pp. 101-134.

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