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NTIS 바로가기IEEE transactions on electron devices, v.68 no.12, 2021년, pp.6106 - 6111
Gupta, Mohit Kumar (IMEC, Heverlee, Belgium) , Weckx, Pieter (IMEC, Leuven, Belgium) , Schuddinck, Pieter (IMEC, Leuven, Belgium) , Jang, Doyoung (IMEC, Leuven, Belgium) , Chehab, Bilal (IMEC, Leuven, Belgium) , Cosemans, Stefan (IMEC, Leuven, Belgium) , Ryckaert, Julien (IMEC, Leuven, Belgium) , Dehaene, Wim (IMEC, Heverlee, Belgium)
This article discusses complementary FET (CFET)-based static random access memory (SRAM) to achieve next-generation bitcell area scaling and performance gain in advanced CMOS technology nodes. SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are mandatory to co...
Proc Symp VLSI Circuits (VLSI Circuits) A 14 nm SoC platform technology featuring 2nd generation tri-gate transistors, 70 nm gate pitch, 52 nm metal pitch, and 0.0499 ?m² SRAM cells, optimized for low power, high performance and high density SoC products jan 2015 12t
Gupta, Mohit Kumar, Weckx, Pieter, Schuddinck, Pieter, Jang, Doyoung, Chehab, Bilal, Cosemans, Stefan, Ryckaert, Julien, Dehaene, Wim. A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node. IEEE transactions on electron devices, vol.68, no.8, 3819-3825.
IEDM Tech Dig Buried bitline for sub-5 nm SRAM design mathur 2020 20.2.1
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IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 7 nm 256 Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications chang 2017 206
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 153 Mb-SRAM design with dynamic stability enhancement and leakage reduction in 45 nm high-K metal-gate CMOS technology hamzaoglu 2008 376
Song, Taejoong, Rim, Woojin, Park, Sunghyun, Kim, Yongho, Yang, Giyong, Kim, Hoonki, Baek, Sanghoon, Jung, Jonghoon, Kwon, Bongjae, Cho, Sungwee, Jung, Hyuntaek, Choo, Yongjae, Choi, Jaeseung. A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. IEEE journal of solid-state circuits, vol.52, no.1, 240-249.
Proc Symp VLSI Technol Comprehensive analysis of variability sources of FinFET characteristics matsukawa 2009 118
IEDM Tech Dig 3-D self-aligned stacked NMOS-on-PMOS nanoribbon transistors for continued Moore’s law scaling huang 2020 20.6.1
Proc Symp VLSI Technol Highly manufacturable 7 nm FinFET technology featuring EUV lithography for low power and high performance applications ha 2017 68t
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