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NTIS 바로가기IEEE transactions on electron devices, v.51 no.10, 2004년, pp.1733 - 1736
Tsui, Bing-Yue (Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan) , Chin, Li-Feng
Fringing-induced barrier lowering (FIBL) effect on nanoscale MOSFET is comprehensively examined. It is observed that by combining stack gate dielectric, conductive spacer, short sidewall spacer, and minimum gate/drain (G/D) overlap, the Ioff with a dielectric constant of (k) 100 is only 1.6 times higher than that with k=3.9 when the gate length is 25 nm. The fully depleted silicon-on-insulator device shows even better FIBL immunity. It is concluded that although the FIBL effect can not be eliminated, it would not an issue beyond the 45-nm technology node.
Tech Dig VLSI Symp ultrathin zro $_{2}$ (or silicate) with high thermal stability for cmos gate applications luo 2001 135
Electronics Letters fringing-induced barrier lowering (fibl) in sub-100-nm mosfets with high- $\kappa$ gate dielectrics yeap 1998 10.1049/el:19980800 34 1150
Proc VLSI-TSA new stack gate insulator structure reduce fibl effect obviously lai 2001 216
Proc Dev Res Conf source-side barrier effects with very high- $\kappa$ dielectrics in 50-nm si mosfets kencke 1999 22
Mohapatra, N.R., Desai, M.P., Narendra, S.G., Rao, V.R.. The effect of high-K gate dielectrics on deep submicrometer CMOS device and circuit performance. IEEE transactions on electron devices, vol.49, no.5, 826-831.
International Technology Roadmap for Semiconductors 2003
Tech Dig VLSI Symp high quality ${\hbox {la}}_{2}{\hbox {o}}_{3}$ and ${\hbox {al}}_{2}{\hbox {o}}_{3}$ gate dielectrics with equivalent oxide thickness 5–10 a chin 2001 13
IEDM Tech Dig effect of polysilicon gate on the flatband voltage shift and mobility degradation for ald- ${\rm al}_{2}{\rm o}_{3}$ gate dielectric lee 2000 645
Choi, C.H., Jeon, T.S., Clark, R., Kwong, D.L.. Electrical properties and thermal stability of CVD HfOxNy gate dielectric with poly-Si gate electrode. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.24, no.4, 215-217.
Rino Choi, Onishi, K., Chang Seok Kang, Hag-Ju Cho, Kim, Y.H., Krishnan, S., Akbar, M.S., Lee, J.C.. Effects of deuterium anneal on MOSFETs with HfO2 gate dielectrics. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.24, no.3, 144-146.
IEDM Tech Dig hfo $_{2}$ and hfalo for cmos: thermal stability and current transport zhu 2001 463
Autran, J.-L., Devine, R., Chaneliere, C., Balland, B.. Fabrication and characterization of Si-MOSFET's with PECVD amorphous Ta2O5 gate insulator. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.18, no.9, 447-449.
Lo, S.-H., Buchanan, D.A., Taur, Y., Wang, W.. Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET's. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.18, no.5, 209-211.
Tech Dig VLSI Symp performance of mosfets with ultrathin zro $_{2}$ and zr silicate gate dielectrics qi 2000 15
Medici Two-Dimensional Device Simulation Program User s Manual 2003
User s Manual for SUPREM Two-Dimensional Process Simulation 2003
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