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Solid-state electronics, v.49 no.2, 2005년, pp.271 - 274
Chen, Qiang (Corresponding author. Tel.) , Wang, Lihui (Microelectronics Research Center, Georgia Institute of Technology, 791 Atlantic Drive NW, Atlanta, GA 30332-0269, USA) , Meindl, James D. (Microelectronics Research Center, Georgia Institute of Technology, 791 Atlantic Drive NW, Atlanta, GA 30332-0269, USA)
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AbstractA physical, compact, short-channel threshold voltage model for undoped double-gate MOSFETs has been extended through a phenomenological approach to include the fringe-induced barrier lowering (FIBL) effect associated with high-permittivity (high-k) gate dielectrics. The resulting analytical ...
IEEE IEDM Tech. Dig. Gusev 451 2001 Ultra-thin high-k gate stacks for advanced CMOS devices
Electron. Lett. Yeap 34 11 1150 1998 10.1049/el:19980800 Fringing-induced barrier lowering (FIBL) in sub-100nm MOSFETs with high-k gate dielectrics
Superlattices Microstruct. Frank 28 5/6 485 2000 10.1006/spmi.2000.0952 Analysis of the design space available for high-k gate dielectrics in nanoscale MOSFETs
IEEE IEDM Tech. Dig. Wong 407 1998 Device design consideration for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25nm channel length generation
Solid-State Electron. Zhang 44 11 2089 2000 10.1016/S0038-1101(00)00152-0 Modeling short channel effect on high-k and stacked-gate MOSFETs
IEEE EDL Liu 23 5 270 2002 10.1109/55.998873 Threshold voltage model for MOSFETs with high-k gate dielectrics
IEEE T-ED Chen 50 7 2003 A physical short-channel threshold voltage model for undoped symmetric double-gate MOSFETs
IEEE T-ED Bowman 48 8 1800 2001 10.1109/16.936710 A circuit-level perspective of the optimum gate oxide thickness
IEEE T-ED Vogel 45 6 1350 1998 10.1109/16.678572 Modeled tunnel currents for high dielectric constant dielectrics
IBM J. Res. Dev. Osburn 46 2/3 299 2002 10.1147/rd.462.0299 Vertically scaled MOSFET gate stacks and junctions: how far are we likely to go
Symp. VLSI Technol. Dig. Harada 26 2002 Specific structural factors influencing on reliability of CVD-HfO2
IEEE IEDM Tech. Dig. Hergenrother 51 2001 50nm vertical replacement-gate (VRG) nMOSFETs with ALD HfO2 and Al2O3 gate dielectrics
Lee JH, Kim YS, Jung HS, Lee JH, Lee NI, Kang HK, et al. Poly-Si gate CMOSFETs with HfO2-Al2O3 laminate gate dielectric for low power applications. Symp VLSI Tech Dig, 2002
Onishi K, Kang CS, Choi R, Cho HJ, Gopalan S, Nieh R, et al. Effects of high-temperature forming gas anneal on HfO2 MOSFET performance. Symp VLSI Tech Dig, 2002
Samavedam SB, Tseng HH, Tobin PJ, Mogab J, Dakshina-Murthy S, La LB, et al. Metal gate MOSFETs with HfO2 gate dielectrics. Symp VLSI Tech Dig, 2002
Pidin S, Morisaki Y, Sugita Y, Aoyama T, Irino K, Nakamura T, et al. Low standby power CMOS with HfO2 gate oxide for 100-nm generation. Symp VLSI Tech Dig, 2002
Proc. IEEE Taur 85 4 486 1997 10.1109/5.573737 CMOS scaling into the nanometer regime
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