참고문헌 (33)

1. McIntyre, H., Wendell, D., Lin, K.J., Kaushik, P., Seshadri, S., Wang, A., Sundararaman, V., Ping Wang, Song Kim, Hsu, W.-J., Hee-Choul Park, Levinsky, G., Jiejun Lu, Chirania, M., Heald, R., Lazar, P., Dharmasena, S.. A 4-MB on-chip L2 cache for a 90-nm 1.6-GHz 64-bit microprocessor. IEEE journal of solid-state circuits, vol.40, no.1, 52-59.

   상세보기

2. 10.1109/DATE.2010.5456940 

   

3. 10.1109/DATE.2007.364490 

   

4. 10.1109/VLSIC.2005.1469357 

   

5. Proc Symp VLSI Circuits Scaling Trends of Cosmic Ray Induced Soft Errors in Static Latches beyond 0.18 2001 61 

6. Suzuki, T., Yamagami, Y., Hatanaka, I., Shibayama, A., Akamatsu, H., Yamauchi, H.. A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme. IEEE journal of solid-state circuits, vol.41, no.1, 152-160.

   상세보기

7. IEEE J Solid-State Circuits Universal-Vdc 0. pp.65–2.0-V 32-kB Cache Using a Voltage-Adapted Timing-Generation Scheme and a Lithographically Symmetrical Cell osada 0 36 

8. Zhang, Kevin, Bhattacharya, U., Chen, Zhanping, Hamzaoglu, F., Murray, D., Vallepalli, N., Wang, Yih, Zheng, Bo, Bohr, M.. A 3-GHz 70-mb SRAM in 65-nm CMOS technology with integrated column-based dynamic power supply. IEEE journal of solid-state circuits, vol.41, no.1, 146-151.

   상세보기

9. Ohbayashi, Shigeki, Yabuuchi, Makoto, Nii, Koji, Tsukamoto, Yasumasa, Imaoka, Susumu, Oda, Yuji, Yoshihara, Tsutomu, Igarashi, Motoshige, Takeuchi, Masahiko, Kawashima, Hiroshi, Yamaguchi, Yasuo, Tsukamoto, Kazuhiro, Inuishi, Masahide, Makino, Hiroshi, Ishibashi, Koichiro, Shinohara, Hirofumi. A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits. IEEE journal of solid-state circuits, vol.42, no.4, 820-829.

   상세보기

10. Proc IEEE Intl Solid-State Circuits Conf A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS khellah 2006 2572 

11. 10.1109/VLSIC.2007.4342741 

    

12. IEEE J Solid-State Circuits A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redun-dancy verma 0 10.1109/JSSC.2007.908005 43 141 

    상세보기

13. Proc IEEE Intl Solid-State Circuits Conf A 300 MHz 25JlAlMb Leakage On-Chip SRAM Module Featuring Process-Variation Immunity and Low-Leakage-Active Mode for Mobile-Phone Application Processor yamaoka 2004 1 494 

14. Proc Symp VLSI Circuits A 45nm 0.6V Cross-Point 8T SRAM with Negative Biased Read/Write Assist yabuuchi 2009 158 

15. Proc 5th Int'l Symp Quality Electronic Design SRAM Leakage Suppression by Minimizing Standby Supply Voltage qin 2004 55 

16. Takeda, K., Hagihara, Y., Aimoto, Y., Nomura, M., Nakazawa, Y., Ishii, T., Kobatake, H.. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications. IEEE journal of solid-state circuits, vol.41, no.1, 113-121.

    상세보기

17. 10.1109/ISSCC.2010.5433818 

    

18. Kwong, J., Ramadass, Y.K., Verma, N., Chandrakasan, A.P.. A 65 nm Sub- $V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter. IEEE journal of solid-state circuits, vol.44, no.1, 115-126.

    상세보기

19. Calhoun, B.H., Chandrakasan, A.P.. A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-Voltage Operation. IEEE journal of solid-state circuits, vol.42, no.3, 680-688.

    상세보기

20. 10.1109/ISSCC.2008.4523215 

    

21. 10.1109/.2005.1469239 

    

22. Wei Zhao, Yu Cao. New Generation of Predictive Technology Model for Sub-45 nm Early Design Exploration. IEEE transactions on electron devices, vol.53, no.11, 2816-2823.

    상세보기

23. Chang, Ik Joon, Kim, Jae-Joon, Park, Sang Phill, Roy, Kaushik. A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE journal of solid-state circuits, vol.44, no.2, 650-658.

    상세보기

24. Sinangil, M.E., Verma, N., Chandrakasan, A.P.. A Reconfigurable 8T Ultra-Dynamic Voltage Scalable (U-DVS) SRAM in 65 nm CMOS. IEEE journal of solid-state circuits, vol.44, no.11, 3163-3173.

    상세보기

25. 10.1109/IEDM.2007.4418976 

    

26. IEEE Int Solid-State Circ Conf (ISSCC Westmere: A Family of 32nm IA Processors kurd 2010 96 

27. Pilo, Harold, Barwin, Charlie, Braceras, Geordie, Browning, Chris, Lamphier, Steve, Towler, Fred. An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage. IEEE journal of solid-state circuits, vol.42, no.4, 813-819.

    상세보기

28. 10.1109/ISSCC.2010.5433816 

    

29. Proc IEEE Int'l Electron Devices Meeting Fluctuation Limits & Scaling Opportunities for CMOS SRAM Cells bhavnagarwala 2005 659 

30. Proc IEEE Int'l Solid-State Circuits Conf 65nm Low-Power High-Density SRAM Operable at 1.OV under 3? Systematic Variation Using Separate Vth Monitoring and Body Bias for NMOS and PMOS yamaoka 2008 384 

31. Pille, J., Adams, C., Christensen, T., Cottier, S.R., Ehrenreich, S., Kono, F., Nelson, D., Takahashi, O., Tokito, S., Torreiter, O., Wagner, O., Wendel, D.. Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V. IEEE journal of solid-state circuits, vol.43, no.1, 163-171.

    상세보기

32. Kim, Tae-Hyoung, Liu, Jason, Keane, John, Kim, Chris H.. A 0.2 V, 480 kb Subthreshold SRAM With 1 k Cells Per Bitline for Ultra-Low-Voltage Computing. IEEE journal of solid-state circuits, vol.43, no.2, 518-529.

    상세보기

33. Cosemans, S., Dehaene, W., Catthoor, F.. A 3.6 pJ/Access 480 MHz, 128 kb On-Chip SRAM With 850 MHz Boost Mode in 90 nm CMOS With Tunable Sense Amplifiers. IEEE journal of solid-state circuits, vol.44, no.7, 2065-2077.

    상세보기