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NTIS 바로가기Procedia Technology, v.25, 2016년, pp.481 - 488
Mariyamol, p.p. , Aswathy, N.
Leakage power dissipation of on-chip SRAM constitutes a significant amount of the total chip power consumption in microprocessors and System on chips. With technology scaling, it is becoming increasingly challenging to maintain the yield while attempting to reduce the leakage power of SRAMs. The sou...
J.B. Kim “Low-Power Digital Circuit Design with Triple-Threshold Voltage” September 2010, Volume 4, No.9 (Serial No.34) Journal of Energy and Power Engineering, ISSN 1934-8975 USA.
IEEE I.S.SC. Li 25 4 1005 1990 CMOS tapered buffer
Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits,” IEEE J. Solid-State Circuits Veendrick SC-19 4 468 1984
10.1109/TCSII.2007.907784 Ahmed Shebaita and Yehea Ismail Multiple Threshold Voltage Design Scheme for CMOS Tapered Buffers IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS-II: EXPRESS BRIEFS, VOL. 55, NO. 1, JANUARY 2008.
HARPREET KAUR*, AJAYPAL SINGH and LIPIKA GUPTA, Department of Electronics and Communication, Chitkara University, Himachal Pradesh-125001, India, FbbCmos Tapered Buffer With Optimal Vth Selection, Journal on Today's Ideas -Tomorrow's Technologies,Vol. 2, No. 1,June 2014pp. 1-13.
Design of CMOS Tapered Buffer for High Speed and Low Power Applications using 65nm Technology International Journal of Science and Research (IJSR) ISSN (Online): 2319-7064 Index Copernicus Value (2013): 6.14 Impact Factor (2013): 4.438.
Mr.AnkurSaxena*, Mr.SumitKhandelwal A Novel Design Approach for CMOS Tapered Buffer for Low Power and Low Delay Applications Volume 2 2015 Issue 4 JULY-AUG IJBRITISH.
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