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電氣學會論文誌. IEEJ Transactions on Electronics, Information and Systems. C : 電子·情報·システム, v.130 no.2, 2010년, pp.226 - 234
菅野 孝一 (湘南工科大学) , 渡辺 (工学) , 重佳 (部情報工学)
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Design technology of stacked NAND type 1-transistor FeRAM has been described. With 39nm design rule feasibility study of 1Tbit memory focused on cell array structure and core circuit has been investigated. 64 layer 8k×8k stacked SGT memory cell array structure and the double ended row and colu...
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