참고문헌 (14)

1. Kral A , Behbahani F , Abidi AA . RF‐CMOS oscillators with switched tuning . IEEE Custom Integrated Circuits Conference , May 1998 ; pp. 555 – 558 . 

2. Hegazi E , Sjoland H , Abidi AA . A filtering technique to lower LC oscillator phase noise . IEEE Journal of Solid‐State Circuits Dec. 2001 ; 35 ( 12 ): 1921 – 1930 . 

3. Jeong C‐Y , Choi D‐H , Yoo C . A fast automatic frequency calibration (AFC) scheme for phase‐locked loop (PLL) frequency synthesizer . IEEE Radio Frequency Integrated Circuits Symposium , Jun. 2009 ; pp. 583 – 586 . 

4. Lin TH , Kaiser WJ . A 900‐MHz 2.5‐mA CMOS frequency synthesizer with an automatic SC tuning loop . IEEE Journal of Solid‐State Circuits Mar. 2001 ; 36 : 424 – 431 . 

   상세보기

5. Aktas A , Ismail M . CMOS PLL calibration techniques . IEEE Circuits Devices Magazine Sept./Oct. 2004 ; 20 ( 5 ): 6 – 11 . 

6. Wilson WB , Moon U , Lakshmikumar KR , Dai L . A CMOS self‐calibrating frequency synthesizer . IEEE Journal of Solid‐State Circuits Oct. 2000 ; 35 ( 10 ): 1437 – 1444 . 

   상세보기

7. Lee H , Cho J , Lee K , Hwang I , Ahn T , Nah K , Park B . A Σ‐Δ fractional‐N frequency synthesizer using a wide‐band integrated VCO and a fast AFC technique for GSM/GPRS/WCDMA applications . IEEE Journal of Solid‐State Circuits Jul. 2004 ; 39 ( 7 ): 1164 – 1169 . 

8. Marutani M , Anbutsu H , Kondo M , Shirai N , Yamazaki H , Watanabe Y . An 18 mW 90 to 770 MHz synthesizer with agile auto‐tuning for digital TV‐tuners . IEEE ISSCC Dig. Tech. Papers , Feb. 2006 ; pp. 192 – 193 . 

9. Lin TH , Lai YJ . An agile VCO frequency calibration technique for a 10‐GHz CMOS PLL . IEEE Journal of Solid‐State Circuits Feb. 2007 ; 42 : 340 – 349 . 

   상세보기

10. Lee J , Kim K , Lee J , Jang T , Cho S . A 480‐MHz to 1 GHz sub‐picosecond clock generator with a fast and accurate automatic frequency calibration in 0.13 µm CMOS . IEEE Asian Solid‐State Circuits Conference , Nov. 2007 ; pp. 67 – 70 . 

11. Li Z , O KK . A low‐phase noise and low‐power multiband CMOS voltage‐controlled oscillator . IEEE Journal of Solid‐State Circuits Jun. 2005 ; 40 ( 6 ): 1296 – 1302 . 

    상세보기

12. Rao A , Mansour M , Singh G , Lim C‐H , Ahmed R , Johnson DR . A 4–6.4 GHz LC PLL with adaptive bandwidth control for a forwarded clock link . IEEE Journal of Solid‐State Circuits Sep. 2008 ; 43 ( 9 ): 2099 – 2107 . 

    상세보기

13. Lee K‐S , Yu H , Ahn HK , Oh H‐S , Ryu S , Keum D , Park B‐H . A 0.13 µm CMOS Σ‐Δ frequency synthesizer with an area optimizing LPF, fast AFC time, and a wideband VCO for WCDMA/GSM/GPRS/EDGE applications . IEEE Radio Frequency Integrated Circuits Symposium , Jun. 2008 ; pp. 299 – 302 . 

14. Lu L , Gong Z , Liao Y , Min H , Tang Z . A 975‐to‐1960 MHz fast‐locking fractional‐N synthesizer with adaptive bandwidth control and 4/4.5 prescaler for digital TV tuners . IEEE Int. Solid‐State Circuits Conf. Dig. Tech. Papers , Feb. 2009 ; pp. 396 – 397 .