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NTIS 바로가기Microelectronic engineering, v.137, 2015년, pp.158 - 163
Kim, S.E. , Kim, S.
Wafer level bonding and stacking process for 3D stacked IC was proposed and technical issues were discussed. Cu bumps surrounded by recessed SiO2 were thermo-compression bonded and electrically evaluated using Kelvin structures. Defects at the bonding interface such as voids were responsible for ele...
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