[논문]3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability

Jaeil Lim; Hyunyul Lim; Sungho Kang

doi:10.1109/TCAD.2015.2413411

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society, v.34 no.9, 2015년, pp.1455 - 1466

Jaeil Lim (Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea) , Hyunyul Lim (Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea) , Sungho Kang (Dept. of Electr. & Electron. Eng., Yonsei Univ., Seoul, South Korea)

Abstract ▼ AI-Helper

The 3-D integrated dynamic random-access memory (DRAM) structure with a processor is being widely studied due to advantages, such as a large band-width and data communication power reduction. In these structures, the massive heat generation of the processor results in a high operating temperature and a high refresh rate of the DRAM. Thus, in the 3-D DRAM over processor architecture, temperature-aware refresh management is necessary. However, temperature determination is difficult, because in the 3-D DRAM, the temperature changes dynamically and temperature variation in a DRAM die is complicated. In this paper, a thermal guard-band set-up method for 3-D stacked DRAM is proposed. It considers the latency of the temperature data and the position difference between the temperature sensor and the DRAM cell. With this method, the data reliability of the on-chip temperature sensor-dependent adaptive refresh control is guaranteed. In addition, an efficient temperature sensor built-in and refresh control method is analyzed. The expected refresh power reduction is examined through a simulation.

주제어

참고문헌 (31)

Lewyn, Lanny L., Ytterdal, Trond, Wulff, Carsten, Martin, Kenneth. Analog Circuit Design in Nanoscale CMOS Technologies. Proceedings of the IEEE, vol.97, no.10, 1687-1714.

상세보기
Souri, K., Makinwa, K. A. A.. A 0.12 mm $^{2}$ 7.4 $\mu$ W Micropower Temperature Sensor With an Inaccuracy of $\pm$0.2 $^{\circ}$C (3 $\sigma$) From $-$30 $^{\circ}$C to 125 $^{\circ}$C. IEEE journal of solid-state circuits, vol.46, no.7, 1693-1700.

상세보기
10.1109/TEST.2008.4700556
2 GB x16 x32 Mobile LPDDR2 SDRAM S4 Features 2010
Various Methods of DRAM Refresh 1999
Jong Sung Lee, Skadron, K., Sung Woo Chung. Predictive Temperature-Aware DVFS. IEEE transactions on computers, vol.59, no.1, 127-133.

상세보기
10.1145/859618.859620
Sharifi, S, Rosing, T S. Accurate Direct and Indirect On-Chip Temperature Sensing for Efficient Dynamic Thermal Management. IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society, vol.29, no.10, 1586-1599.

상세보기
10.1109/IITC.2009.5090331
Tobita, Takao, Kasahara, Hironori. A standard task graph set for fair evaluation of multiprocessor scheduling algorithms. Journal of scheduling, vol.5, no.5, 379-394.

상세보기
Proc IEEE Int Solid-State Circuits Conf (ISSCC) A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth jain 2001 240
Nawathe, U.G., Hassan, M., Yen, K.C., Kumar, A., Ramachandran, A., Greenhill, D.. Implementation of an 8-Core, 64-Thread, Power-Efficient SPARC Server on a Chip. IEEE journal of solid-state circuits, vol.43, no.1, 6-20.

상세보기
Souri, K., Youngcheol Chae, Makinwa, K. A. A.. A CMOS Temperature Sensor With a Voltage-Calibrated Inaccuracy of $\pm$ 0.15 $ ^{\circ}$ C (3 $\sigma$ ) From $-$ 55 $^{\circ}$ C to 125 $^{\circ}$ C. IEEE journal of solid-state circuits, vol.48, no.1, 292-301.

상세보기
Proc Int Symp Comput Archit (ISCA) RAIDR: Retention-aware intelligent DRAM refresh liu 2012 10.1145/2366231.2337161 1

상세보기
Young-Jae An, Kyungho Ryu, Dong-Hoon Jung, Seung-Han Woo, Seong-Ook Jung. An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management. IEEE sensors journal, vol.14, no.1, 104-110.

상세보기
10.1109/MICRO.2007.13
10.1109/CoolChips.2014.6842950
10.1109/CAS-ICTD.2009.4960775
10.1145/1815961.1815973
10.1109/ISCAS.2011.5937902
10.1109/VLSIC.1993.920531
10.1109/IGCC.2011.6008579
Proc Design Autom Test Eur Conf Exhibition (DATE) Energy optimization in 3D MPSoCs with wide-I/O DRAM using temperature variation aware bank-wise refresh sadri 2014 1
10.1109/ISCA.2008.15
10.1145/1669112.1669172
Calculating Memory System Power for DDR3 2007
2 GB x16 x32 Mobile LPDDR2 SDRAM S4 Features 2011
10.1109/ICDE.2004.1320032
10.1109/ISCA.2008.16
Nangate 45nm open cell library 2008
Austin, T., Larson, E., Ernst, D.. SimpleScalar: an infrastructure for computer system modeling. Computer, vol.35, no.2, 59-67.

상세보기

LOADING...

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 논문명, 저널/프로시딩명, 저자 , 발행년, 권, 호, 시작페이지, 끝페이지, 발행기관 관리번호, 논문명, 대등논문명, 저자 , 저널/프로시딩명, 발행기관, 발행년, 발행언어, 권, 호, 시작페이지, 끝페이지, ISBN, ISSN, 주제분야, 키워드, 초록(한글), 초록(영문), 저자(소속기관)
저장형식	Text(ASCII format) Excel format RefWorks Direct Export RIS format (for Reference Manager, ProCite, EndNote), Scholar's Aids, Mendeley
메일정보	받는사람 (필수) @ 보내는사람 (선택) @ 제목 내용 KISTI 검색결과 이메일 서비스
안내	총 건의 자료가 검색되었습니다. 다운받으실 자료의 인덱스를 입력하세요. (1-10,000) 검색결과의 순서대로 최대 10,000건 까지 다운로드가 가능합니다. 데이타가 많을 경우 속도가 느려질 수 있습니다.(최대 2~3분 소요) 다운로드 파일은 UTF-8 형태로 저장됩니다. 파일의 내용이 제대로 보이지 않을실 때는 웹브라우저 상단의 보기 -> 인코딩 -> 자동선택 여부를 확인하십시오. ~ Text(ASCII format) Excel format

연합인증

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability

Abstract ▼ AI-Helper

주제어

참고문헌 (31)

이 논문을 인용한 문헌

연구과제 타임라인

관련 콘텐츠

원문 URL 링크

이 논문과 함께 이용한 콘텐츠

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트

연합인증

3-D Stacked DRAM Refresh Management With Guaranteed Data Reliability

Abstract ▼ AI-Helper

주제어

참고문헌 (31)

이 논문을 인용한 문헌

연구과제 타임라인

전체(0) 논문(0) 특허(0) 보고서(0)

전체(0) 논문(0) 특허(0) 보고서(0)

관련 콘텐츠

원문 URL 링크

이 논문과 함께 이용한 콘텐츠

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

선택된 텍스트