Mil’shtein, Samson
(Advanced Electronic Technology Center, ECE Department, University of Massachusetts, Lowell, MA, 01854, USA)
,
Devarakonda, Lalitha
(Advanced Electronic Technology Center, ECE Department, University of Massachusetts, Lowell, MA, 01854, USA)
,
Zanchi, Brian
(Advanced Electronic Technology Center, ECE Department, University of Massachusetts, Lowell, MA, 01854, USA)
,
Palma, John
(Advanced Electronic Technology Center, ECE Department, University of Massachusetts, Lowell, MA, 01854, USA)
The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and...
The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.
The tendency to have better control of the flow of electrons in a channel of field-effect transistors (FETs) did lead to the design of two gates in junction field-effect transistors, field plates in a variety of metal semiconductor field-effect transistors and high electron mobility transistors, and finally a gate wrapping around three sides of a narrow fin-shaped channel in a FinFET. With the enhanced control, performance trends of all FETs are still challenged by carrier mobility dependence on the strengths of the electrical field along the channel. However, in cases when the ratio of FinFET volume to its surface dramatically decreases, one should carefully consider the surface boundary conditions of the device. Moreover, the inherent non-planar nature of a FinFET demands 3D modeling for accurate analysis of the device performance. Using the Silvaco modeling tool with quantization effects, we modeled a physical FinFET described in the work of Hisamoto et al. (IEEE Tran. Elec. Devices 47:12, 2000) in 3D. We compared it with a 2D model of the same device. We demonstrated that 3D modeling produces more accurate results. As 3D modeling results came close to experimental measurements, we made the next step of the study by designing a dual-gate FinFET biased at Vg1 >Vg2. It is shown that the dual-gate FinFET carries higher transconductance than the single-gate device.
Hisamoto D Lee W Kedzierski J Takeuchi H Asano K Kuo C Anderson E King T Bokor J Chenming H FinFET - a self-aligned double-gate MOSFET scalable to 20 nm IEEE T Electron Dev 2000 47 12
Choi YJ Choi BY Kim KR Lee JD Park B-G A new 50 nm n-MOSFET with side-gates for virtual source-drain extensions IEEE T Electron Dev 2002 49 1833 1835 10.1109/TED.2002.803648
Wong H-SP Chan KK Taur Y Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel Technical Digest. International: Dec 7-10 1997;Washington DC 1997 New York: IEEE 427 430
Mil’shtein S Shaping electric field in heterostructure transistors Microelectron J 2005 36 319 322 10.1016/j.mejo.2005.02.053
Jurczak M Collaert N Veloso A Hoffmann T Biesemans S Review of FinFET technology Proc. 2009 Int. SOI Conference: Oct 5-8 2009;Foster City,CA 2009 New York: IEEE 1 4
Yu B Chang L Ahmed S Wang H Bell S Yang C-H Tabery C Ho C Xiang Q King T-J Bokor J Hu C Lin M-R Kyser D FinFET scaling to 10 nm gate length Tech. Dig. 2002 Int. Electron Devices Meeting 2002: Dec 8-11 2002; San Francisco,CA 2002 New York: IEEE 251 254
Put S Simoen E Jurczak M Van Uffelen M Leroux P Claeys C Influence of fin width on the total dose behavior of p-channel bulk MuGFETs Electron Device Lett 2010 31 243 245
Mil’shtein S Palma J FinFET with constant transconductance Microelectron Solid-State Electron 2012 1 2 21 25
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