$\require{mediawiki-texvc}$

연합인증

연합인증 가입 기관의 연구자들은 소속기관의 인증정보(ID와 암호)를 이용해 다른 대학, 연구기관, 서비스 공급자의 다양한 온라인 자원과 연구 데이터를 이용할 수 있습니다.

이는 여행자가 자국에서 발행 받은 여권으로 세계 각국을 자유롭게 여행할 수 있는 것과 같습니다.

연합인증으로 이용이 가능한 서비스는 NTIS, DataON, Edison, Kafe, Webinar 등이 있습니다.

한번의 인증절차만으로 연합인증 가입 서비스에 추가 로그인 없이 이용이 가능합니다.

다만, 연합인증을 위해서는 최초 1회만 인증 절차가 필요합니다. (회원이 아닐 경우 회원 가입이 필요합니다.)

연합인증 절차는 다음과 같습니다.

최초이용시에는
ScienceON에 로그인 → 연합인증 서비스 접속 → 로그인 (본인 확인 또는 회원가입) → 서비스 이용

그 이후에는
ScienceON 로그인 → 연합인증 서비스 접속 → 서비스 이용

연합인증을 활용하시면 KISTI가 제공하는 다양한 서비스를 편리하게 이용하실 수 있습니다.

[해외논문] Highly Biased Linear Condition Method for Separately Extracting Source and Drain Resistance in MOSFETs

IEEE transactions on electron devices, v.65 no.2, 2018년, pp.419 - 423  

Kim, Gun-Hee (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea) ,  Bae, Hagyoul (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea) ,  Hur, Jae (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea) ,  Kim, Choong-Ki (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea) ,  Lee, Geon-Beom (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea) ,  Bang, Tewook (SK hynix Inc., Icheon, South Korea) ,  Son, Yoon-Ik (SK hynix Inc., Icheon, South Korea) ,  Ryu, Seong-Wan (SK hynix Inc., Icheon, South Korea) ,  Choi, Yang-Kyu (School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea)

Abstract AI-Helper 아이콘AI-Helper

A highly biased linear current method (HBLCM) for separately extracting source and drain resistance ( ${R}_{S}$ and ${R}_{D}$) in MOSFETs is proposed. The technique can be applied to a single device by using simple modeling. Compared to other methods, it provides accurate value...

참고문헌 (21)

  1. Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.. Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE transactions on electron devices, vol.52, no.6, 1132-1140.

  2. Hagyoul Bae, Seok Cheon Baek, Sunyeong Lee, Jaeman Jang, Ja Sun Shin, Daeyoun Yun, Hyojong Kim, Dae Hwan Kim, Dong Myong Kim. Separate Extraction of Source, Drain, and Substrate Resistances in MOSFETs With Parasitic Junction Current Method. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.31, no.11, 1190-1192.

  3. Lou, Choon-Leong, Chim, Wai-Kin, Chan, D.S.-H., Pan, Tang. A novel single-device DC method for extraction of the effective mobility and source-drain resistances of fresh and hot-carrier degraded drain-engineered MOSFET's. IEEE transactions on electron devices, vol.45, no.6, 1317-1323.

  4. Kim, Jaewon, Lee, Heesung, Kim, Seong Kwang, Kim, Junyeap, Park, Jaewon, Choi, Sung-Jin, Kim, Dae Hwan, Kim, Dong Myong. Hybrid Open Drain Method and Fully Current-Based Characterization of Asymmetric Resistance Components in a Single MOSFET. IEEE transactions on electron devices, vol.63, no.11, 4196-4200.

  5. Solid State Electron Experimental determination of short-channel MOSFET parameters hao 1985 28 1025 

  6. Lin, Po-Yen, Chiu, Yu-Lun, Sung, Yuh-Te, Chen, Jim, Chang, Tzong-Sheng, King, Ya-Chin, Lin, Chrong Jung. On-Chip Recovery Operation for Self-Aligned Nitride Logic Non-Volatile Memory Cells in High-K Metal Gate CMOS Technology. IEEE journal of the Electron Devices Society, vol.3, no.6, 463-467.

  7. Luryi Choi, Byoung Hak Hong, Young Chai Jung, Keun Hwi Cho, Kyoung Hwan Yeo, Dong-Won Kim, Gyo Young Jin, Kyung Seok Oh, Won-Seong Lee, Sang-Hun Song, Jae Sung Rieh, Dong Mok Whang, Sung Woo Hwang. Extracting Mobility Degradation and Total Series Resistance of Cylindrical Gate-All-Around Silicon Nanowire Field-Effect Transistors. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.30, no.6, 665-667.

  8. Jin He, Xing Zhang, Yangyuan Wang, Ru Huang. New method for extraction of MOSFET parameters. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.22, no.12, 597-599.

  9. Samudra, G.S, Seah, B.P, Ling, C.H. Determination of LDD MOSFET drain resistance from device simulation. Solid-state electronics, vol.39, no.5, 753-758.

  10. Pan, Y., Ng, K.K., Wei, C.C.. Hot-carrier induced electron mobility and series resistance degradation in LDD NMOSFET's. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.15, no.12, 499-501.

  11. 10.1109/IEDM.2015.7409775 

  12. Lee, Minjoo L., Fitzgerald, Eugene A., Bulsara, Mayank T., Currie, Matthew T., Lochtefeld, Anthony. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. Journal of applied physics, vol.97, no.1, 011101-.

  13. Raychaudhuri, A., Kolk, J., Deen, M.J., King, M.I.H.. A simple method to extract the asymmetry in parasitic source and drain resistances from measurements on a MOS transistor. IEEE transactions on electron devices, vol.42, no.7, 1388-1390.

  14. Taur, Y., Zicherman, D.S., Lombardi, D.R., Restle, P.J., Hsu, C.H., Nanafi, H.I., Wordeman, M.R., Davari, B., Shahidi, G.G.. A new 'shift and ratio' method for MOSFET channel-length extraction. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.13, no.5, 267-269.

  15. Hagyoul Bae, Jaeman Jang, Ja Sun Shin, Daeyoun Yun, Jieun Lee, Tae Wan Kim, Dae Hwan Kim, Dong Myong Kim. Modeling and Separate Extraction of Gate-Bias- and Channel-Length-Dependent Intrinsic and Extrinsic Source–Drain Resistances in MOSFETs. IEEE electron device letters : a publication of the IEEE Electron Devices Society, vol.32, no.6, 722-724.

  16. 10.1109/MWSYM.1994.335220 

  17. IEEE Electron Device Lett Mobility enhancement in surface channel SiGe PMOSFETs with HfO2 gate dielectrics shi 2003 24 34 

  18. Fischetti, M. V., Laux, S. E.. Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys. Journal of applied physics, vol.80, no.4, 2234-2252.

  19. IEEE Electron Device Lett Dual-sweep combinational transconductance technique for separate extraction of parasitic resistances in amorphous thin-film transistors jun 2015 36 144 

  20. Jun-Young Park, Dong-Il Moon, Myeong-Lok Seol, Choong-Ki Kim, Chang-Hoon Jeon, Hagyoul Bae, Tewook Bang, Yang-Kyu Choi. Self-Curable Gate-All-Around MOSFETs Using Electrical Annealing to Repair Degradation Induced From Hot-Carrier Injection. IEEE transactions on electron devices, vol.63, no.3, 910-915.

  21. Chang-Hoon Jeon, Jun-Young Park, Myeong-Lok Seol, Dong-Il Moon, Jae Hur, Hagyoul Bae, Seung-Bae Jeon, Yang-Kyu Choi. Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor. IEEE transactions on electron devices, vol.63, no.6, 2288-2292.

LOADING...
섹션별 컨텐츠 바로가기

AI-Helper ※ AI-Helper는 오픈소스 모델을 사용합니다.

AI-Helper 아이콘
AI-Helper
안녕하세요, AI-Helper입니다. 좌측 "선택된 텍스트"에서 텍스트를 선택하여 요약, 번역, 용어설명을 실행하세요.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.

선택된 텍스트

맨위로