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IEEE transactions on electron devices, v.65 no.3, 2018년, pp.881 - 887
Jaiswal, Nivedita (Low Power Nanoelectronics Research Group, Discipline of Electrical Engineering, IIT Indore, Indore, India) , Kranti, Abhinav (Low Power Nanoelectronics Research Group, Discipline of Electrical Engineering, IIT Indore, Indore, India)
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In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double...
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