최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기IEEE journal of solid-state circuits, v.54 no.1, 2019년, pp.217 - 230
Biswas, Avishek (Kilby Labs, Texas Instruments Incorporated, Dallas, TX, USA) , Chandrakasan, Anantha P. (Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA, USA)
This paper presents an energy-efficient static random access memory (SRAM) with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell-based SRAM array is used to store the 1-b filter weights. The array implements dot-product as a weighted averag...
Sze, Vivienne, Chen, Yu-Hsin, Yang, Tien-Ju, Emer, Joel S.. Efficient Processing of Deep Neural Networks: A Tutorial and Survey. Proceedings of the IEEE, vol.105, no.12, 2295-2329.
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers Computing’s energy problem (and what we can do about it) horowitz 2014 10
IEEE ISSCC Dig Tech Papers Conv-RAM: An energy-efficient SRAM with embedded convolution computation for low-power CNN-based machine learning applications biswas 2018 488
Zhang, Jintao, Wang, Zhuo, Verma, Naveen. In-Memory Computation of a Machine-Learning Classifier in a Standard 6T SRAM Array. IEEE journal of solid-state circuits, vol.52, no.4, 915-924.
Kang, Mingu, Gonugondla, Sujan K., Patil, Ameya, Shanbhag, Naresh R.. A Multi-Functional In-Memory Inference Processor Using a Standard 6T SRAM Array. IEEE journal of solid-state circuits, vol.53, no.2, 642-655.
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 42 pJ/decision 3.12 TOPS/W robust in-memory machine learning classifier with on-chip training gonugondla 2018 490
Ando, Kota, Ueyoshi, Kodai, Orimo, Kentaro, Yonekawa, Haruyoshi, Sato, Shimpei, Nakahara, Hiroki, Takamaeda-Yamazaki, Shinya, Ikebe, Masayuki, Asai, Tetsuya, Kuroda, Tadahiro, Motomura, Masato. BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W. IEEE journal of solid-state circuits, vol.53, no.4, 983-994.
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8 TOPS/W fully parallel product-sum operation for binary DNN edge processors khwa 2018 496
Lecun, Y., Bottou, L., Bengio, Y., Haffner, P.. Gradient-based learning applied to document recognition. Proceedings of the IEEE, vol.86, no.11, 2278-2324.
Chen, Yu-Hsin, Krishna, Tushar, Emer, Joel S., Sze, Vivienne. Eyeriss: An Energy-Efficient Reconfigurable Accelerator for Deep Convolutional Neural Networks. IEEE journal of solid-state circuits, vol.52, no.1, 127-138.
Proc Adv Neural Inf Process Syst ImageNet classification with deep convolutional neural networks krizhevsky 2012 1097
Moons, Bert, Verhelst, Marian. An Energy-Efficient Precision-Scalable ConvNet Processor in 40-nm CMOS. IEEE journal of solid-state circuits, vol.52, no.4, 903-914.
Proc Adv Neural Inf Process Syst Binarized neural networks hubara 2016 4107
Proc Adv Neural Inf Process Syst BinaryConnect: Training deep neural networks with binary weights during propagations courbariaux 2015 3123
Hinton, G., Li Deng, Dong Yu, Dahl, G. E., Mohamed, A., Jaitly, N., Senior, Andrew, Vanhoucke, V., Nguyen, P., Sainath, T. N., Kingsbury, B.. Deep Neural Networks for Acoustic Modeling in Speech Recognition: The Shared Views of Four Research Groups. IEEE signal processing magazine, vol.29, no.6, 82-97.
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers A 28 nm SoC with a 1.2 GHz 568 nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applications whatmough 2017 242
Energy-efficient smart embedded memory design for IoT and AI biswas 2018
IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers Envision: A 0.26-to-10 TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI moons 2017 246
Chuhong Duan, Gotterba, Andreas J., Sinangil, Mahmut E., Chandrakasan, Anantha P.. Energy-Efficient Reconfigurable SRAM: Reducing Read Power Through Data Statistics. IEEE journal of solid-state circuits, vol.52, no.10, 2703-2711.
Proc Eur Solid-State Circuits Conf (ESSCIRC) A 0.36 V 128 Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28 nm FDSOI biswas 2016 433
*원문 PDF 파일 및 링크정보가 존재하지 않을 경우 KISTI DDS 시스템에서 제공하는 원문복사서비스를 사용할 수 있습니다.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.