PHOTOLITHOGRAPHY PROCESS AND PHOTOLITHOGRAPHY APPARATUS
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
G03F-001/44
G03F-001/36
G03F-001/00
G03F-001/26
H01L-021/027
G03F-007/20
출원번호
US-0101631
(2018-08-13)
공개번호
US-0064655
(2019-02-28)
우선권정보
CN-201710734995.8 (2017-08-24)
발명자
/ 주소
DU, Yao Jun
LI, Liang
LIU, Juan
출원인 / 주소
DU, Yao Jun
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A photolithography process includes providing a first test layout including test patterns, and a first light source; forming an initial mask layout according to the first test layout; forming a mask layout including mask layout patterns through an optical proximity correction or a phase-shifting mas
A photolithography process includes providing a first test layout including test patterns, and a first light source; forming an initial mask layout according to the first test layout; forming a mask layout including mask layout patterns through an optical proximity correction or a phase-shifting masking; forming exposed patterns by exposing the mask layout using the first light source; and determining a weak region from the first test layout. A first distance between adjacent test patterns in the weak region is unequal to a second distance between corresponding exposed patterns. The photolithography process further includes performing a re-layout on the weak region to increase the first distance, thereby providing an adjusted test layout; performing a light-source optimization to obtain an adjusted light source; and determining the adjusted test layout and the adjusted light source as a second test layout and a second light source, respectively when process window requirements are satisfied.
대표청구항▼
1. A photolithography process, comprising: providing a first test layout and a first light source, the first test layout including a plurality of test patterns; andforming a mask layout according to the first test layout, including: forming an initial mask layout according to the first test layout,
1. A photolithography process, comprising: providing a first test layout and a first light source, the first test layout including a plurality of test patterns; andforming a mask layout according to the first test layout, including: forming an initial mask layout according to the first test layout, wherein the initial mask layout is substantially same as or proportional to the first test layout, andperforming at least one of an optical proximity correction (OPC) and a phase-shifting masking (PSM) on the initial mask layout to form the mask layout, wherein the mask layout includes a plurality of mask layout patterns;forming a plurality of exposed patterns by exposing the mask layout using the first light source;determining a weak region, including a plurality of test patterns, from the first test layout, wherein a distance between adjacent test patterns in the weak region is a first distance, a distance between adjacent exposed patterns that correspond to the test patterns is a second distance, and the first distance is unequal to the second distance;performing a re-layout on the weak region to increase the first distance between adjacent test patterns in the weak region, thereby providing an adjusted test layout;performing a light-source optimization to obtain an adjusted light source according to the adjusted test layout; anddetermining the adjusted test layout as a second test layout and the adjusted light source as a second light source when requirements by a photolithography process window are satisfied using the adjusted test layout and the adjusted light source. 2. The photolithography process according to claim 1, wherein: the mask layout is substantially same as the first test layout or proportional to the first test layout with a ratio. 3. The photolithography process according to claim 1, wherein: the at least one of the OPC and the PSM is performed multiple times on the initial mask layout. 4. The photolithography process according to claim 1, wherein the re-layout of the weak region includes: acquiring a distance incremental amount of the first distance between adjacent test patterns; andincreasing the first distance between adjacent test patterns in the weak region by the distance incremental amount. 5. The photolithography process according to claim 4, wherein: the distance incremental amount is acquired by performing finite-difference computation based on the exposed patterns and the test patterns. 6. The photolithography process according to claim 1, wherein: the re-layout of the weak region is performed multiple times on the weak region. 7. The photolithography process according to claim 1, wherein determining the weak region of the first test layout includes: acquiring the first distance between adjacent test patterns of the first test layout and acquiring the second distance between the adjacent exposed patterns that correspond to the test patterns; andwhen the first distance is unequal to the second distance, a region of the first test layout containing the adjacent test patterns is determined as the weak region. 8. The photolithography process according to claim 7, wherein: when the first distance is smaller than the second distance, the region of the first test layout containing the adjacent test patterns is determined as the weak region. 9. The photolithography process according to claim 1, further including: repeatedly performing: forming the mask layout according to the first test layout, forming the plurality of exposed patterns, determining the weak region, performing the re-layout on the weak region, and performing the light-source optimization, such that the requirements by the photolithography process window using the adjusted test layout and the adjusted light source are satisfied. 10. The photolithography process according to claim 9, wherein: the requirements by the photolithography process window is satisfied when the photolithography process window is greater than a preset value. 11. The photolithography process according to claim 1, further including: after obtaining the second light source by performing the light-source optimization, the second test layout is obtained according to the second light source. 12. The photolithography process according to claim 1, wherein: the light-source optimization includes adjusting one or more of a light source distribution, a light intensity, and a exposure time, wherein the light-source optimization is performed using a method based on one of a genetic algorithm and a particle swarm optimization (PSO) algorithm to adjust the one or more of the light source distribution, the light intensity, and the exposure time. 13. The photolithography process according to claim 1, further including: providing a to-be-formed layout and a base substrate, wherein the to-be-formed layout includes a replacement region substantially same as the weak region of the first test layout, and the weak region of the first test layout that is substantially identical to the replacement region is an identical region;determining a region in the second test layout that corresponds to the identical region as an optimization region, and forming an optimized layout by replacing the replacement region in the to-be-formed layout with the optimization region;acquiring a chip mask plate according to the optimized layout; andexposing the base substrate using the second light source through the chip mask plate to form a photolithographic pattern on the base substrate. 14. The photolithography process according to claim 13, wherein acquiring the chip mask plate according to the optimized layout includes: forming an initial chip mask layout according to the optimized layout, wherein the initial chip mask layout is substantially same as or proportional to the optimized layer with a ratio;performing a chip-mask optimization on the initial chip mask layout to obtain a chip mask layout; andforming the chip mask plate according to the chip mask layout. 15. The photolithography process according to claim 14, wherein: the light-source optimization is performed using a method based on one of a genetic algorithm and a PSO algorithm. 16. The photolithography process according to claim 13, wherein: the base substrate includes a substrate and a photoresist layer formed on the substrate. 17. A photolithography apparatus, comprising: an input device, configured to provide a first test layout and a first light source, wherein the first test layout includes a plurality of test patterns;a mask layout formation device, configured to form a mask layout according to the first test layout;an exposure device, configured to form a plurality of exposed patterns by exposing the mask layout using the first light source;a weak region acquisition device, configured to obtain a weak region including a plurality of test patterns in the first test layout, wherein a distance between adjacent test patterns in the weak region is a first distance, a distance between adjacent exposed patterns that correspond to the test patterns is a second distance, and the first distance is unequal to the second distance;a re-layout device, configured to increase the distance between adjacent test patterns in the weak region by performing a re-layout one or multiple times on the weak region; anda light-source optimization device, configured to perform a light-source optimization one or multiple times on the light source according to the first test layout. 18. The photolithography apparatus according to claim 17, wherein the mask layout formation device further includes: an initial chip mask layout formation device, configured to form an initial chip mask layout according to the first test layout; anda mask optimization device, configured to form the mask layout by performing a mask optimization one or multiple times on the initial chip mask layout, wherein the mask layout includes a plurality of mask patterns. 19. The photolithography apparatus according to claim 17, wherein re-layout device further includes: a differential device, configured to acquire a distance incremental amount through finite-difference computation performed based on the exposed patterns and the test patterns; andan increase device, configured to increase the distance between adjacent test patterns in the weak region, such that the distance between adjacent test patterns is increased by the distance incremental amount.
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