[미국특허]
DIRECT DRIVE RF CIRCUIT FOR SUBSTRATE PROCESSING SYSTEMS
원문보기
IPC분류정보
국가/구분
United States(US) Patent
공개
국제특허분류(IPC7판)
H01J-037/32
H03K-005/135
출원번호
16007481
(2018-06-13)
공개번호
20190385821
(2019-12-19)
발명자
/ 주소
LONG, Maolin
Paterson, Alexander
출원인 / 주소
LONG, Maolin
인용정보
피인용 횟수 :
0인용 특허 :
0
초록▼
A direct drive circuit for providing RF power to a component of a substrate processing system includes a clock generator to generate a clock signal at a first frequency, a gate driver to receive the clock signal and a half bridge circuit. The half bridge circuit includes a first switch with a contro
A direct drive circuit for providing RF power to a component of a substrate processing system includes a clock generator to generate a clock signal at a first frequency, a gate driver to receive the clock signal and a half bridge circuit. The half bridge circuit includes a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal; a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal; a first DC supply to supply a first voltage potential to the first terminal of the first switch; and a second DC supply to supply a second voltage potential to the second terminal of the second switch. The first voltage potential and the second voltage potential have opposite polarity and are approximately equal in magnitude.
대표청구항▼
1. (canceled) 2. A direct drive circuit for providing RF power to a component of a substrate processing system, comprising: a clock generator to generate a clock signal at a first frequency;a gate driver to receive the clock signal;a half bridge circuit including: a first switch with a control termi
1. (canceled) 2. A direct drive circuit for providing RF power to a component of a substrate processing system, comprising: a clock generator to generate a clock signal at a first frequency;a gate driver to receive the clock signal;a half bridge circuit including: a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal;a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal;a first DC supply to supply a first voltage potential to the first terminal of the first switch; anda second DC supply to supply a second voltage potential to the second terminal of the second switch, wherein the first voltage potential and the second voltage potential have opposite polarity and are approximately equal in magnitude;a current sensor to sense current at the output node and to generate a current signal;a voltage sensor to sense a voltage at the output node and to generate a voltage signal; anda controller including: a phase offset calculator to calculate a phase offset between the voltage signal and the current signal; anda clock adjuster to adjust the first frequency based on the phase offset. 3. The direct drive circuit of claim 2, wherein the clock adjuster increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current. 4. (canceled) 5. A direct drive circuit for providing RF power to a component of a substrate processing system, comprising: a clock generator to generate a clock signal at a first frequency;a gate driver to receive the clock signal;a half bridge circuit including: a first switch with a control terminal connected to the gate driver, a first terminal and a second terminal;a second switch with a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal;a first DC supply to supply a first voltage potential to the first terminal of the first switch; anda second DC supply to supply a second voltage potential to the second terminal of the second switch, wherein the first voltage potential and the second voltage potential have opposite polarity and are approximately equal in magnitude;a first circuit connecting the output node to the component of the substrate processing system, wherein the first circuit includes:a first capacitor connected to the output node; anda first inductor connected in series with the first capacitor;the first circuit further includes: a second inductor having a first terminal connected to the output node;a third inductor having a first terminal connected to a second terminal of the second inductor;a second capacitor connected in parallel with the second inductor; anda third capacitor having a first terminal connected to the second terminal of the third inductor. 6. (canceled) 7. A dual frequency drive circuit comprising: the direct drive circuit of claim 2; andan additional drive circuit connected to the component of the substrate processing system and operating at a second frequency that is different than the first frequency. 8. The dual frequency drive circuit of claim 7, wherein the additional drive circuit includes a second one of the direct drive circuit. 9. The dual frequency drive circuit of claim 7, wherein the additional drive circuit includes an RF generator generating an RF signal at the second frequency. 10. The dual frequency drive circuit of claim 9, wherein the additional drive circuit further includes an output circuit including a matching circuit to match an impedance of the RF generator to the component. 11. The dual frequency drive circuit of claim 10, wherein the output circuit includes: a first inductor connected to an output of the RF generator;a second inductor; anda first variable capacitor having a first terminal connected to the output of the RF generator and a second terminal connected to the second inductor. 12. The dual frequency drive circuit of claim 11, wherein the output circuit further includes: a third inductor having a first terminal connected to the output;a second variable capacitor having a first terminal connected to a second terminal of the third inductor;a fourth inductor having a first terminal connected to a second terminal of the second variable capacitor; anda first capacitor having a first terminal connected to a second terminal of the fourth inductor and a second terminal connected to the component. 13. A drive circuit for providing RF power to a component of a substrate processing system, comprising: a first direct drive circuit connected to the component of the substrate processing system and including: a first clock generator to generate a first clock signal at a first frequency;a first gate driver to receive the first clock signal;a first half bridge circuit connected between the first gate driver and a first output node, the first half bridge circuit biased by a first DC supply and a second DC supply, wherein a first voltage potential supplied by the first DC supply and a second voltage potential supplied by the second DC supply have opposite polarity and are approximately equal in magnitude; anda first blocking circuit to connect the first output node to the component of the substrate processing system and to block a second frequency that is different than the first frequency; anda second drive circuit connected to the component of the substrate processing system and operating at the second frequency. 14. The drive circuit of claim 13, further comprising: a current sensor to sense current at the first output node and to generate a current signal;a voltage sensor to sense a voltage at the first output node and to generate a voltage signal;a controller including: a phase offset calculator to calculate a phase offset between the voltage signal and the current signal; anda clock adjuster to adjust the first frequency based on the phase offset. 15. The drive circuit of claim 14, wherein the clock adjuster increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current. 16. The drive circuit of claim 13, wherein the first blocking circuit includes: a first capacitor connected to the first output node; anda first inductor connected in series with the first capacitor. 17. The drive circuit of claim 16, wherein the first blocking circuit further includes: a second inductor having a first terminal connected to the first output node;a third inductor having a first terminal connected to a second terminal of the second inductor;a second capacitor connected in parallel with the second inductor; anda third capacitor having a first terminal connected to the second terminal of the third inductor. 18. The drive circuit of claim 13, wherein the second drive circuit includes an RF generator to generate an RF signal at the second frequency. 19. The drive circuit of claim 18, wherein the second drive circuit further includes a first output circuit including an adjustable matching circuit to match an impedance of the RF generator to the component. 20. The drive circuit of claim 19, wherein the first output circuit includes: a first inductor connected to the RF generator;a second inductor; anda first variable capacitor having a first terminal connected to the RF generator and a second terminal connected to the second inductor. 21. The drive circuit of claim 20, wherein the first output circuit further includes: a third inductor having a first terminal connected to the RF generator;a second variable capacitor having a first terminal connected to a second terminal of the third inductor;a fourth inductor having a first terminal connected to a second terminal of the second variable capacitor; anda first capacitor having a first terminal connected to a second terminal of the fourth inductor and a second terminal connected to the component. 22. The drive circuit of claim 14, wherein the second drive circuit includes: a second clock generator to generate a second clock signal at the second frequency;a second gate driver to receive the second clock signal;a second half bridge circuit including a second half bridge circuit connected between the second gate driver and a second output node, the second half bridge circuit biased by a third DC supply and a fourth DC supply, wherein a first voltage potential supplied by the third DC supply and a second voltage potential supplied by the fourth DC supply have opposite polarity and are approximately equal in magnitude; anda second blocking circuit to connect the second output node to the component of the substrate processing system and to block the first frequency.
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