The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor
The present disclosure provides methods of fabricating a semiconductor device. A method according to one embodiment includes forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material, forming a semiconductor cap layer over the first fin and the second fin, and annealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed.
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1. A method, comprising: forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material;forming a semiconductor cap layer over the first fin and the second fin; andannealing the
1. A method, comprising: forming, on a substrate, a first fin formed of a first semiconductor material and a second fin formed of a second semiconductor material different from the first semiconductor material;forming a semiconductor cap layer over the first fin and the second fin; andannealing the semiconductor cap layer at a first temperature while at least a portion of the semiconductor cap layer is exposed. 2. The method of claim 1, wherein the first fin comprises a p-type channel region,wherein the second fin comprises an n-type channel region,wherein the first semiconductor material comprises germanium,wherein the second semiconductor material comprises silicon. 3. The method of claim 1, wherein the semiconductor cap consists essentially of silicon. 4. The method of claim 1, wherein the first temperature is greater than 800° C. 5. The method of claim 1, wherein the first temperature is between about 800° C. and about 1050° C. 6. The method of claim 1, wherein the forming of the semiconductor cap layer comprises depositing silicon using atomic layer deposition (ALD). 7. The method of claim 1, wherein the forming of the semiconductor cap layer comprises epitaxially growing silicon over the first fin and the second fin. 8. The method of claim 1, wherein the annealing of the semiconductor cap layer increases crystallinity of the semiconductor cap layer. 9. A method, comprising: forming, on a substrate, a first fin comprising silicon and germanium;forming, on the substrate, a second fin comprising silicon;forming a silicon cap layer over the first fin and the second fin;performing a first anneal at a first temperature and a first pressure while at least a portion of the silicon cap layer is exposed;forming source/drain features over source/drain regions of the first fin and the second fin;forming a gate structure over channel regions of the first fin and the second fin; andafter the forming of the gate structure, performing a second anneal at a second temperature and a second pressure while no portion of the silicon cap layer is exposed. 10. The method of claim 9, wherein the first temperature is greater than the second temperature,wherein the second pressure is greater than the first temperature. 11. The method of claim 9, wherein a germanium content in the first fin is between about 20% and about 60%. 12. The method of claim 9, wherein the forming of the silicon cap layer comprises depositing silicon using atomic layer deposition (ALD). 13. The method of claim 9, wherein the forming of the silicon cap layer comprises epitaxially growing silicon over the first fin and the second fin. 14. The method of claim 9, wherein the first temperature is between about 800° C. and about 1050° C.,wherein the first pressure is between about 0.01 atmosphere (atm) and about 1.1 atm. 15. The method of claim 9, wherein the second temperature is between about 350° C. and about 450° C.,wherein the second pressure is between about 10 atmosphere (atm) and about 20 atm. 16. The method of claim 9, wherein the gate structure comprises a high-k dielectric layer, a work function layer, and a metal fill layer. 17. A method, comprising: forming, on a substrate, a first fin comprising silicon and germanium;forming, on the substrate, a second fin comprising silicon;forming a silicon cap layer over the first fin and the second fin; andimmediately after the forming of the silicon cap layer, performing a first anneal at a temperature between about 800° C. and about 1050° C. 18. The method of claim 17, wherein the forming of the silicon cap layer comprises depositing silicon using atomic layer deposition (ALD). 19. The method of claim 17, wherein the forming of the silicon cap layer comprises epitaxially growing silicon over the first fin and the second fin. 20. The method of claim 17, further comprising: forming a gate structure over channel regions of the first fin and the second fin; andafter the forming of the gate structure, performing a second anneal at a temperature between about 350° C. and about 450° C.
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