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Nonvolatile memory device with NAND array 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G11C-007/00
출원번호 US-0293915 (1994-08-22)
우선권정보 JP-0216623 (1993-08-31); JP-0323896 (1993-12-22)
발명자 / 주소
  • Nobukata Hiromi (Kanagawa JPX) Satori Kenichi (Kanagawa JPX)
출원인 / 주소
  • Sony Corporation (Tokyo JPX 03)
인용정보 피인용 횟수 : 30  인용 특허 : 0

초록

A semiconductor nonvolatile memory device which enables shortening of the time of the bit verification operation and thus high speed reading operations, including a first memory cell array connected to a first bit line, a second memory cell array connected to a second bit line, a first transistor op

대표청구항

A semiconductor nonvolatile memory device, comprising: first and second bit lines; a first memory cell array connected to said first bit line; a second memory cell array connected to said second bit line; a latch type sense amplifier having a first and second node for holding complementary levels; a

이 특허를 인용한 특허 (30)

  1. Pascucci Luigi,ITX, Circuit for detecting the coincidence between a binary information unit stored therein and an external datum.
  2. Park,Hee Sik; Lee,Kyeong Bock; Park,Byung Soo, Flash memory device.
  3. Okazawa,Takeshi, Magnetic memory device having XP cell and Str cell in one chip.
  4. Pascucci Luigi,ITX, Method for verifying electrically programmable non-volatile memory cells of an electrically programmable non-volatile me.
  5. Kwak, Donghun, Method of programming a 3-dimensional nonvolatile memory device based on a program order of a selected page and a location of a string selection line.
  6. Lu,Qiang; Fastow,Richard; Wang,Zhigang, Method, system, and circuit for performing a memory related operation.
  7. Choi Jung-Dal,KRX, Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same.
  8. Choi Jung-Dal,KRX, Multi-bit memory cell array of a non-volatile semiconductor memory device and method for driving the same.
  9. Hazama,Hiroaki; Ootani,Norio, NAND type memory with dummy cells adjacent to select transistors being biased at different voltage during data erase.
  10. Gomez, Kevin Arthur; Steiner, Michael Joseph; Gaertner, Mark Allen; Goss, Ryan James, Non-volatile buffering to enable sloppy writes and fast write verification.
  11. Satori Kenichi,JPX ; Nobukata Hiromi,JPX, Non-volatile semiconductor memory device using folded bit line architecture.
  12. Arase Kenshiro,JPX, Nonvolatile memory array with NAND string memory cell groups selectively connected to sub bit lines.
  13. In,Ji hyun; Lee,Kwang yoon; Yoon,Song ho, Nonvolatile memory device and method for storing status information using multiple strings.
  14. Akira Hosogane JP, Nonvolatile semiconductor memory device capable of correctly performing erasure/programming completion determination even in presence of defective bit.
  15. Hazama,Hiroaki; Ohtani,Norio, Nonvolatile semiconductor memory device having configuration of NAND strings with dummy memory cells adjacent to select transistors.
  16. Kang,Dong Ku; Byeon,Dae Seok; Lim,Young Ho, Nonvolatile semiconductor memory device having uniform operational characteristics for memory cells.
  17. Hazama, Hiroaki; Ohtani, Norio, Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell.
  18. Hazama, Hiroaki; Ohtani, Norio, Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell.
  19. Hazama, Hiroaki; Ohtani, Norio, Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell.
  20. Hazama, Hiroaki; Ohtani, Norio, Nonvolatile semiconductor memory device including plural memory cells and a dummy cell coupled to an end of a memory cell.
  21. Derner, Scott; Kurth, Casey; Wald, Phillip G., ROM embedded DRAM with bias sensing.
  22. Jo, Sung Kyu; Choi, Yun Ho, Self-reference sense amplifier circuit and sensing method.
  23. Abiko, Naofumi; Yoshihara, Masahiro, Semiconductor memory device.
  24. Hwang, Soon-Wook; Park, Ki-Tae; Lee, Yeong-Taek, Semiconductor memory device.
  25. Lancaster Loren T., Semiconductor reference voltage generator having a non-volatile memory structure.
  26. Sato,Kazuo, Semiconductor storage device.
  27. Li,Kris X.; Guo,Jason; Hui,Edward S., Sense amplifier for flash memory device.
  28. Moschiano, Violante; Santin, Giovanni; Vali, Tommaso, Sensing scheme in a memory device.
  29. Lee, Jong-Ho, Simplified nonvolatile memory cell string and NAND flash memory array using the same.
  30. Terence G. W. Blake ; Bernhard H. Andresen ; Frederick G. Wall, Voltage level shifter with testable cascode devices.
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