이 특허를 인용한 특허 (173)

1. Ruesch,Rodney, Anticipatory programmable interface pre-driver.

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2. Petrie, William, Apparatus and method for modeling coarse stepsize delay element and delay locked loop using same.

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3. Patrick J. Mullarkey, Apparatus for adjusting delay of a clock signal relative to a data signal.

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4. Farooq, Rizwan M., Arrangement for generating multiple clocks in field programmable gate arrays of a network test system.

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5. Shen Feng ; Tsai Kunlin, Circuit and method for reducing delay line length in delay-locked loops.

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6. Schmidt Hartmut,DEX, Circuit arrangement for generating two signals staggered in time from a clock signal and for measuring their time stagge.

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7. Wildes, Paul T.; Birrittella, Mark S., Circuit design for high-speed digital communication.

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8. Yoon, Yong-Jin; Cho, Uk-Rae; Park, Jung-Woo; Lee, Kwang-Jin; Kim, Nam-Seog, Circuits and methods for generating internal clock signal of intermediate phase relative to external clock.

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9. Sung Jun Bae,KRX, Clock phase correction circuit.

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10. Busch Robert Edward (Essex Junction VT) Zick Kenneth Michael (Dallas TX) Houle Robert Maurice (Williston VT), Clock synchronization scheme for fractional multiplication systems.

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11. Keeth Brent, Clock vernier adjustment.

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12. Keeth Brent, Clock vernier adjustment.

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13. Takanori Saeki JP, Combinational delay circuit for a digital frequency multiplier.

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14. Patrick J. Mullarkey, Computer system having memory device with adjustable data clocking.

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15. Mullarkey, Patrick J., Computer system having memory device with adjustable data clocking using pass gates.

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16. Rokugawa Hiroyuki,JPX, Data identifying device and light receiver using the same.

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17. Rokugawa Hiroyuki,JPX, Data identifying device and light receiver using the same.

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18. Tanaka Akira,JPX ; Doi Toshio,JPX ; Ishibashi Kenichi,JPX ; Hayashi Takehisa,JPX ; Yamagiwa Akira,JPX, Data transfer apparatus fetching reception data at maximum margin of timing.

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19. Kumata Ichiro,JPX, Delay circuit and oscillator circuit using the same.

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20. Nguyen, Andy T.; Zhou, Shi-dong, Delay lock loop using shift register with token bit to select adjacent clock signals.

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21. Haerle, Dieter; Mai, Tony; Vlasenko, Peter, Delay locked loop circuit and method.

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22. Haerle, Dieter; Mai, Tony; Vlasenko, Peter, Delay locked loop circuit and method.

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23. Haerle, Dieter; Mai, Tony; Vlasenko, Peter, Delay locked loop circuit and method.

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24. Haerle,Dieter; Mai,Tony; Vlasenko,Peter, Delay locked loop circuit and method.

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25. Foss, Richard C.; Gillingham, Peter B.; Allan, Graham, Delay locked loop implementation in a synchronous dynamic random access memory.

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26. Foss, Richard C.; Gillingham, Peter B.; Allan, Graham, Delay locked loop implementation in a synchronous dynamic random access memory.

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27. Foss, Richard C.; Gillingham, Peter B.; Allan, Graham, Delay locked loop implementation in a synchronous dynamic random access memory.

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28. Foss,Richard C.; Gillingham,Peter B.; Allan,Graham, Delay locked loop implementation in a synchronous dynamic random access memory.

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29. Manning Troy A., Delay-locked loop with binary-coupled capacitor.

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30. Manning Troy A., Delay-locked loop with binary-coupled capacitor.

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31. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.

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32. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.

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33. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.

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34. Troy A. Manning, Delay-locked loop with binary-coupled capacitor.

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35. Foss Richard C.,CAX ; Gillingham Peter B.,CAX ; Allan Graham,CAX, Delayed locked loop implementation in a synchronous dynamic random access memory.

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36. Foss Richard C.,CAX ; Gillingham Peter B.,CAX ; Allan Graham,CAX, Delayed locked loop implementation in a synchronous dynamic random access memory.

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37. Foss Richard C.,CAX ; Gillingham Peter B.,CAX ; Allan Graham,CAX, Delayed locked loop implementation in a synchronous dynamic random access memory.

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38. Foss, Richard C.; Gillingham, Peter B.; Allan, Graham, Delayed locked loop implementation in a synchronous dynamic random access memory.

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39. Foss, Richard C.; Gillingham, Peter B.; Allan, Graham, Delayed locked loop implementation in a synchronous dynamic random access memory.

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40. Fang,Al; Farrell,Mike; Butka,Brian, Delayed-locked loop with fine and coarse control using cascaded phase interpolator and variable delay circuit.

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41. Yoneda Satoshi,JPX, Digital PLL circuit.

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42. Bruce Millar CA, Digital delay locked loop.

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43. Millar Bruce,CAX, Digital delay locked loop.

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44. Song Hongjiang, Digital delay locked loop for adaptive de-skew clock generation.

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45. Torbey Elie, Digital phase-locked loop circuit with reduced phase jitter frequency.

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46. Gauvin Coralyn S. ; Petty William K. ; Herbert Brian K., Dual path asynchronous delay circuit.

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47. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.

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48. Lee, Terry R.; Jeddeloh, Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.

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49. Lee,Terry R.; Jeddeloh,Joseph M., Dynamic synchronization of data capture on an optical or other high speed communications link.

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50. Hartwell, David; Donaldson, Darrell, Enhanced clock forwarding data recovery.

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51. Andresen Bernhard H. ; Schenck Stephen R., Free running digital phase lock loop.

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52. Farwell William D., Frequency independent clock synchronizer.

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53. Rosen,Eitan, High resolution digital delay circuit for PLL and DLL.

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54. Rosen,Eitan, High resolution digital delay circuit for PLL and DLL.

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55. Ruesch, Rodney; Jenkins, Philip N.; Ma, Nan, I/O impedance controller.

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56. Mai, Tony, Initialization circuit for delay locked loop.

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57. Kenichi Kawasaki JP; Yasuharu Sato JP; Terumasa Kitahara JP; Masao Nakano JP; Masao Taguchi JP; Yoshihiro Takemae JP; Yasurou Matsuzaki JP; Koichi Nishimura JP; Yoshinori Okajima JP; Naoharu, Input/output data synchronizing device.

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58. Sikkink,Mark Ronald; Huffman,William A.; Swanson,Vernon W.; Ma,Nan; Passint,Randal S., Interface for synchronous data transfer between domains clocked at different frequencies.

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59. Lin, Feng, Interleaved delay line for phase locked and delay locked loops.

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60. Lin, Feng, Interleaved delay line for phase locked and delay locked loops.

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61. Lin,Feng, Interleaved delay line for phase locked and delay locked loops.

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62. Lin,Feng, Interleaved delay line for phase locked and delay locked loops.

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63. Mai, Tony, Intialization circuit for delay locked loop.

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64. Gomm,Tyler J., Measure controlled delay with duty cycle control.

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65. Keeth, Brent, Memory system with dynamic timing correction.

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66. Sauder, Mark F.; Anderson, Michael L.; Fromm, Eric C., Method and apparatus for accessing MMR registers distributed across a large asic.

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67. Baker Russel Jacob ; Manning Troy A., Method and apparatus for adaptively adjusting the timing of a clock signal used to latch digital signals, and memory device using same.

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68. Keeth Brent, Method and apparatus for adaptively adjusting the timing offset between a clock signal and digital signals transmitted coincident with that clock signal, and memory device and system using same.

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69. Mullarkey Patrick J., Method and apparatus for adjusting data timing by delaying clock signal.

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70. Keeth Brent ; Manning Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.

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71. Keeth, Brent; Manning, Troy A., Method and apparatus for adjusting the timing of signals over fine and coarse ranges.

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72. Brent Keeth ; Terry R. Lee ; Kevin Ryan ; Troy A. Manning, Method and apparatus for bit-to-bit timing correction of a high speed memory bus.

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73. Keeth, Brent; Lee, Terry R.; Ryan, Kevin; Manning, Troy A., Method and apparatus for bit-to-bit timing correction of a high speed memory bus.

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74. Arneson,Michael R.; Bowman,Terrance L.; Cornett,Frank N.; DeRyckere,John F.; Hillert,Brian T.; Jenkins,Philip N.; Ma,Nan; Placek,Joseph M.; Ruesch,Rodney; Thorson,Gregory M., Method and apparatus for communicating computer data from one point to another over a communications medium.

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75. Saeki Takanori,JPX, Method and apparatus for controlling clock signals.

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76. Dreps Daniel Mark ; Masleid Robert Paul ; Muhich John Stephen, Method and apparatus for coupled phase locked loops.

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77. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.

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78. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.

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79. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.

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80. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.

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81. Harrison, Ronnie M., Method and apparatus for generating a phase dependent control signal.

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82. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.

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83. Harrison,Ronnie M., Method and apparatus for generating a phase dependent control signal.

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84. Harrison Ronnie M., Method and apparatus for generating a sequence of clock signals.

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85. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.

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86. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.

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87. Harrison, Ronnie M., Method and apparatus for generating a sequence of clock signals.

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88. Harrison,Ronnie M., Method and apparatus for generating a sequence of clock signals.

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89. Troy A. Manning, Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal.

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90. Manning, Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.

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91. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.

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92. Manning,Troy A., Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.

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93. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.

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94. Troy A. Manning, Method and apparatus for generating expect data from a captured bit pattern, and memory device using same.

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95. Brent Keeth, Method and apparatus for high speed data capture utilizing bit-to-bit timing correction, and memory device using same.

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96. Haerle,Dieter; Mai,Tony; Vlasenko,Peter, Method and apparatus for initializing a delay locked loop.

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97. Gasparik, Frank; Smith, Paul J., Method and apparatus for multi-channel data delay equalization.

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98. Ma, Yantao, Method and apparatus for reducing oscillation in synchronous circuits.

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99. Ma, Yantao, Method and apparatus for reducing oscillation in synchronous circuits.

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100. Ma, Yantao, Method and apparatus for reducing oscillation in synchronous circuits.

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101. Manning Troy A., Method and apparatus for resynchronizing a plurality of clock signals used in latching respective digital signals applied to a packetized memory device.

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102. Troy A. Manning, Method and apparatus for resynchronizing a plurality of clock signals used to latch respective digital signals, and memory device using same.

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103. Solomon, Doug; Eiriksson, Asgeir T.; Koren, Yuval; Kaldani, Givargis G., Method and cache-coherence system allowing purging of mid-level cache entries without purging lower-level cache entries.

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104. Fromm, Eric C.; Ruesch, Rodney, Method and circuit for reliable data capture in the presence of bus-master changeovers.

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105. Johnson, Brian; Harrison, Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.

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106. Johnson,Brian; Harrison,Ronnie M., Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same.

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107. Lin, Feng; Keeth, Brent; Johnson, Brian, Method and system for delay control in synchronization circuits.

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108. Collins Hansel Anthony ; Everhardt Paul ; Parry David ; Chesson Greg, Method and system for deskewing parallel bus channels.

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109. Manning, Troy A., Method for generating expect data from a captured bit pattern, and memory device using same.

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110. Lee,Seonghoon, Multi-phase clock signal generator and method having inherently unlimited frequency capability.

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111. Lee,Seonghoon, Multi-phase clock signal generator and method having inherently unlimited frequency capability.

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112. Saeki Takanori,JPX, Multiplex synchronous delay circuit.

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113. Brandt William P., Network switching system including a zero-delay output buffer.

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114. Lin, Feng; Baker, R. Jacob, Phase detector for all-digital phase locked and delay locked loops.

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115. Lin,Feng; Baker,R. Jacob, Phase detector for all-digital phase locked and delay locked loops.

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116. Lin,Feng; Baker,R. Jacob, Phase detector for all-digital phase locked and delay locked loops.

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117. Lin, Feng, Phase detector for reducing noise.

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118. Lin,Feng, Phase detector for reducing noise.

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119. Lin,Feng, Phase detector for reducing noise.

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120. Lin,Feng, Phase detector for reducing noise.

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121. Lee Sang-bo,KRX ; Lee Jae-hyoong,KRX, Phase locked loop integrated circuits having dynamic phase locking characteristics and methods of operating same.

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122. Lee Sang-bo,KRX, Phase locked loop integrated circuits having fuse-enabled and fuse-disabled delay devices therein.

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123. Hinz,Torsten; Jakobs,Andreas; Zaryouh,Benaissa, Phase shifter.

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124. Bhullar, Gurpreet; Allan, Graham, Process, voltage, temperature independent switched delay compensation scheme.

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125. Bhullar, Gurpreet; Allan, Graham, Process, voltage, temperature independent switched delay compensation scheme.

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126. Bhullar, Gurpreet; Allan, Graham, Process, voltage, temperature independent switched delay compensation scheme.

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127. Bhullar,Gurpreet; Allan,Graham, Process, voltage, temperature independent switched delay compensation scheme.

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128. Albert Manhee Chu ; Daniel Mark Dreps ; Frank David Ferraiolo ; Kevin Charles Gower ; Roger Paul Gregor, Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay element.

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129. DeRyckere, John F.; Jenkins, Philip Nord; Cornett, Frank Nolan, Programmable differential delay circuit with fine delay adjustment.

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130. John F. DeRyckere ; Philip Nord Jenkins ; Frank Nolan Cornett, Programmable differential delay circuit with fine delay adjustment.

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131. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., Programmable logic integrated circuit with on-chip DLL or PLL for clock distribution.

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132. Takada Shuichi,JPX ; Yoshizawa Akihiko,JPX, Ring oscillator type voltage controlled oscillator.

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133. Kawasaki Kenichi,JPX ; Sato Yasuharu,JPX ; Kitahara Terumasa,JPX ; Nakano Masao,JPX ; Taguchi Masao,JPX ; Takemae Yoshihiro,JPX ; Matsuzaki Yasurou,JPX ; Nishimura Koichi,JPX ; Okajima Yoshinori,JPX , Semiconductor device, semiconductor system, and digital delay circuit.

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134. Taguchi Masao,JPX ; Takemae Yoshihiro,JPX, Semiconductor device, semiconductor system, and digital delay circuit.

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135. Lu, Hung-Wen; Su, Chau-Chin, Signal delay circuit.

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136. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, Sleep mode initialization in a distributed computing system.

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137. Mansur,Daniel C., Spacial derivative bus encoder and decoder.

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138. Harrison Ronnie M. ; Keeth Brent, Synchronous clock generator including a compound delay-locked loop.

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139. Harrison Ronnie M., Synchronous clock generator including a delay-locked loop signal loss detector.

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140. Harrison Ronnie M., Synchronous clock generator including a false lock detector.

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141. Mullarkey Patrick J., Synchronous memory device having an adjustable data clocking circuit.

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142. Jenkins, Philip Nord; Cornett, Frank N., System and method for adaptively deskewing parallel data signals relative to a clock.

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143. Jenkins,Philip Nord; Cornett,Frank N., System and method for adaptively deskewing parallel data signals relative to a clock.

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144. Jenkins,Philip Nord; Cornett,Frank N., System and method for adaptively deskewing parallel data signals relative to a clock.

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145. Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.

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146. Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.

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147. Lin, Feng, System and method for skew compensating a clock signal and for capturing a digital signal using the skew compensated clock signal.

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148. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.

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149. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.

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150. James,Ralph, System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding.

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151. Lin, Feng, System and method of operation of DLL and PLL to provide tight locking with large range, and dynamic tracking of PVT variations using interleaved delay lines.

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152. Lin, Feng, System and method to provide tight locking for DLL and PLL with large range, and dynamic tracking of PVT variations using interleaved delay lines.

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153. Chengson David P. ; Collins Hansel A. ; Priest Edward C. ; Alvarez Scott W., System and method to reduce jitter in digital delay-locked loops.

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154. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.

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155. Chall, Louis Edmund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.

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156. Chall, Louis Edumund; Serson, John Bradley; Roberts, Philip Arnold; Hutchins, Cecil Eugene, System clock distribution in a distributed computing environment.

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157. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., System for distributing clocks using a delay lock loop in a programmable logic circuit.

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158. Jefferson David E. ; Cope L. Todd,MYX ; Reddy Srinivas ; Cliff Richard G., System for distributing clocks using a delay lock loop in a programmable logic circuit.

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159. Casal Humberto Felipe ; Li Hehching Harry ; Nguyen Trong Duc, Three state phase detector.

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160. Christopher G. Arcus, Twisted-ring oscillator and delay line generating multiple phases using differential dividers and comparators to match delays.

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161. Gomm, Tyler J., Variable delay circuit and method, and delay locked loop, memory device and computer system using same.

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162. Gomm, Tyler J., Variable delay circuit and method, and delay locked loop, memory device and computer system using same.

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163. Gomm, Tyler J., Variable delay circuit and method, and delay locked loop, memory device and computer system using same.

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164. Robert R. Livolsi, Variable delay element for jitter control in high speed data links.

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165. Minzoni,Alessandro, Variable delay line using two blender delays.

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166. Cornett, Frank N.; Jenkins, Philip N.; Bowman, Terrance L.; Placek, Joseph M.; Thorson, Gregory M., Variable mode bi-directional and uni-directional computer communication system.

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167. Vlasenko, Peter; Haerle, Dieter, Wide frequency range delay locked loop.

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168. Vlasenko, Peter; Haerle, Dieter, Wide frequency range delay locked loop.

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169. Vlasenko, Peter; Haerle, Dieter, Wide frequency range delay locked loop.

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170. Vlasenko, Peter; Haerle, Dieter, Wide frequency range delay locked loop.

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171. Vlasenko,Peter; Haerle,Dieter, Wide frequency range delay locked loop.

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172. Lee, Kyeongho; Park, Joonbae, Zero-delay buffer circuit for a spread spectrum clock system and method therefor.

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173. Lee,Kyeongho; Park,Joonbae, Zero-delay buffer circuit for a spread spectrum clock system and method therefor.

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