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Process for etching a semiconductor lead frame 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/48
출원번호 US-0489319 (1995-06-12)
우선권정보 JP-0154323 (1994-06-14); JP-0080906 (1996-03-14)
발명자 / 주소
  • Yamada Junichi (Tokyo JPX)
출원인 / 주소
  • Dai Nippon Printing Co., Ltd. (JPX 03)
인용정보 피인용 횟수 : 71  인용 특허 : 3

초록

A method for producing a lead frame having outer leads and inner leads, for use in constructing a resin-sealed semiconductor package comprises etching processes for etching a blank. A first resist pattern having a first opening and a second resist pattern having second openings are formed on the fir

대표청구항

A method for producing a lead frame having a plurality of outer leads and a plurality of inner leads respectively having tips, for a resin-sealed semiconductor package, comprising: coating a first and a second major surface of a blank for a lead frame with a first and a second photoresist layer, res

이 특허에 인용된 특허 (3)

  1. Cusack Michael D. (Monument CO), Method for densifying leadframe conductor spacing.
  2. Fogelson Harry J. (San Jose CA), Method for manufacturing fine pitch lead frame.
  3. Jarvis Charles R. (Hockley GBX), Preparation of fragile devices.

이 특허를 인용한 특허 (71)

  1. Casati,Paolo; Maierna,Amedeo; Murari,Bruno, Assembly structure for electronic power integrated circuit formed on a semiconductor die and corresponding manufacturing process.
  2. Davis, Terry W.; Son, Sun Jin, Conformal shield on punch QFN semiconductor package.
  3. Berry, Christopher J., Dual laminate package structure with embedded elements.
  4. Berry, Christopher J.; Scanlan, Christopher M.; Faheem, Faheem F., Etch singulated semiconductor package.
  5. Ishikura Junri,JPX ; Yoshikawa Toshiaki,JPX, Etching process.
  6. Fritzsche, Robert M.; Abbott, Donald C., Fine pitch lead frame.
  7. Robert M. Fritzsche ; Donald C. Abbott, Fine pitch lead frame and method.
  8. Choi, YeonHo; Olson, Timothy L., Flat semiconductor package with half package molding.
  9. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  10. Choi, YeonHo; Kim, GiJeong; Kim, WanJong, Fusion quad flat semiconductor package.
  11. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  12. Kim, Gi Jeong; Choi, Yeon Ho; Kim, Wan Jong, Increased I/O leadframe and semiconductor device including same.
  13. Lee, Chang Deok; Na, Do Hyun, Increased I/O semiconductor package and method of making same.
  14. Yang,Sung Jin; Moon,Doo Hwan; Shin,Won Dai, Increased capacity leadframe and semiconductor package using the same.
  15. Kim, Jae Yoon; Kim, Gi Jeong; Moon, Myung Soo, Increased capacity semiconductor package.
  16. Glenn, Thomas P., Integrated circuit package and method of making the same.
  17. Glenn, Thomas P., Integrated circuit package and method of making the same.
  18. Glenn, Thomas P., Integrated circuit package and method of making the same.
  19. Glenn, Thomas P., Integrated circuit package and method of making the same.
  20. Glenn, Thomas P., Integrated circuit package and method of making the same.
  21. Alberghini, John; Kierse, Oliver, Integrated circuit package with enlarged die paddle.
  22. Do, Byung Tai; Trasporto, Arnel Senosa; Chua, Linda Pei Ee; Yusof, Asri, Integrated circuit packaging system with routable traces and method of manufacture thereof.
  23. Lee, Hyung Ju, Leadframe for semiconductor package.
  24. Kuo, Bob Shih Wei; Nickelsen, Jr., John Merrill; Olson, Timothy L., Leadframe structure for concentrated photovoltaic receiver package.
  25. Yang,Sung Jin; Moon,Doo Hwan, Manufacturing method for leadframe and for semiconductor package using the leadframe.
  26. Kim Yung-joon,KRX, Method for lead frame etching.
  27. Brintzinger,Axel; Trovarelli,Octavio, Method for protecting the redistribution layer on wafers/chips.
  28. Frechette Raymond A. ; Sullivan Christopher M., Method of forming flat inner lead tips on lead frame.
  29. Moehle Paul R. ; Kelleher Harold T. ; Lokhorst Gijsbert Willem,NLX, Method of forming lead frames with preformation support.
  30. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  31. Jeon, Hyeong Il; Chung, Hyung Kook; Kim, Hong Bae; Kim, Byong Jin, Micro lead frame structure having reinforcing portions and method.
  32. Samples, Benjamin A., Multi-layer thick-film RF package.
  33. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  34. Roa, Fernando; St. Amand, Roger D., Package in package device for RF transceiver module.
  35. Kang, Dae Byoung; Yang, Sung Jin; Ok, Jung Tae; Kim, Jae Dong, Package in package semiconductor device.
  36. Hwang, Chan Ha; Sohn, Eun Sook; Choi, Ho; Kim, Byong Jin; Yu, Ji Yeon; Lee, Min Woo, Package in package semiconductor device with film over wire.
  37. Yamada Junichi,JPX, Process for etching a semiconductor lead frame.
  38. Samples, Benjamin A., RF package.
  39. Kim, Bong Chan; Kim, Do Hyung; Hwang, Chan Ha; Lee, Min Woo; Sohn, Eun Sook; Kang, Won Joon, Reduced profile stackable semiconductor package.
  40. Kim, Bong Chan; Na, Jae Young; Song, Jae Kyu, Reduced size stacked semiconductor package and method of making the same.
  41. Abbott, Donald C., Selective planishing method for making a semiconductor device.
  42. Hashimoto, Nobuaki, Semiconductor device and film carrier tape.
  43. Arakawa Sadayoshi,JPX ; Ito Seiichi,JPX ; Nishiyama Kenichi,JPX ; Maruyama Koei,JPX, Semiconductor device and method of manufacturing the same.
  44. Hashimoto Nobuaki,JPX, Semiconductor device and methods of manufacturing film camera tape.
  45. Kim, Gwang Ho; Kim, Jin Seong; Park, Dong Joo; Kang, Dae Byoung, Semiconductor device including increased capacity leadframe.
  46. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  47. Kim, Gi Jeong; Choi, Yeon Ho, Semiconductor device including leadframe having power bars and increased I/O.
  48. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands.
  49. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  50. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  51. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  52. Bae, Jae Min; Kim, Byong Jin; Bang, Won Bae, Semiconductor device including leadframe with a combination of leads and lands and method.
  53. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  54. Choi, Yeon Ho; Kim, GiJeong; Kim, WanJong, Semiconductor device including leadframe with increased I/O.
  55. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  56. Kim, Gi Jeong; Kim, Wan Jong, Semiconductor device with increased I/O leadframe.
  57. Kim, Wan Jong; Do, Young Tak; Cho, Byong Woo, Semiconductor device with increased I/O leadframe including power bars.
  58. Kim, Hong Bae; Kim, Hyun Jun; Chung, Hyung Kook, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  59. Kim, Hyun Jun; Chung, Hyung Kook; Kim, Hong Bae, Semiconductor device with leadframe configured to facilitate reduced burr formation.
  60. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  61. Jeon, Hyung Il; Chung, Ji Young; Kim, Byong Jin; Park, In Bae; Bae, Jae Min; Park, No Sun, Semiconductor package and method therefor.
  62. St. Amand, Roger D.; Perelman, Vladimir, Semiconductor package with fast power-up cycle and method of making same.
  63. Lee, Chang Deok; Na, Do Hyun, Semiconductor package with half-etched locking features.
  64. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making same.
  65. Park, Doo Hyun; Kim, Jae Yoon; Jung, Yoon Ha, Semiconductor package with increased I/O density and method of making the same.
  66. Kim, Do Hyeong; Kim, Bong Chan; Kim, Yoon Joo; Chung, Ji Young, Semiconductor package with patterning layer and method of making same.
  67. Choi, Yeon Ho, Side leaded, bottom exposed pad and bottom exposed lead fusion quad flat semiconductor package.
  68. Kim, Yoon Joo; Kim, In Tae; Chung, Ji Young; Kim, Bong Chan; Kim, Do Hyung; Ha, Sung Chul; Lee, Sung Min; Song, Jae Kyu, Stacked semiconductor package and method of making same.
  69. Kim, Ji Yun; Shin, Hyun Sub; Lee, Sung Won; Lee, Hyung Eui; Seo, Yeong Uk; Ryu, Sung Wuk; Lee, Hyuk Soo, Structure for multi-row lead frame and semiconductor package capable of minimizing an under-cut.
  70. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
  71. Berry, Christopher J.; Scanlan, Christopher M., Thin stacked interposer package.
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